Dual-Thickness Gate Oxide Fabrication for SONOS Memory and Logic Integration
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Solution Overview
Problem
Existing methods for fabricating merging semiconductor integrated circuits with both non-volatile SONOS memory devices and logic/analog devices face challenges in achieving dual-thickness gate oxides, as the cleaning and oxidizing processes can alter the thickness of the ONO stacked layer, deteriorating the electric performance of the SONOS memory device.
Innovation Solution
A method where a first gate oxide layer is formed on a substrate covering high voltage, memory, and logic/analog regions, then patterned to define specific channel areas, followed by forming an ONO structure on the memory region and a second gate oxide layer on the logic/analog region, adjusting the processing sequence to prevent thermal impact on the ONO structure, allowing for distinct gate oxide layers with different dielectric constants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a top SiOx layer is formed to cover the SONOS memory region, then the gate oxide thickness for memory devices is optimized, but the cleaning and oxidizing processes dramatically alter the thickness of the top SiOx layer, reducing the processing window and deteriorating the electric performance of the SONOS memory device
Solution Approach 1:
The invention divides the gate oxide formation into two separate stages: first forming a thick gate oxide layer (60-100nm) for high voltage devices, then forming a thin gate oxide layer (10-30nm) for logic/analog devices. This segmentation allows each region to have optimized gate oxide thickness without mutual interference, eliminating the need for a top SiOx layer that would be affected by cleaning and oxidizing processes.
Solution Approach 2:
The thick gate oxide layer for high voltage devices is formed first before any other processing steps. This preliminary action ensures that the gate oxide thickness for high voltage devices is established and protected from subsequent processing, preventing thickness alterations that would occur if formed later in the process sequence.
2Ease of manufacture
If cleaning and oxidizing processes are applied to form gate oxide layers, then the gate oxide is formed on the substrate, but these processes dramatically alter the thickness of the top SiOx layer, reducing the processing window
Solution Approach 1:
The gate oxide formation is segmented into two independent processes: first gate oxide layer formation for high voltage devices, and second gate oxide layer formation for logic/analog devices. This eliminates the need for a top SiOx layer that would be subjected to cleaning and oxidizing processes, thereby preserving the processing window of the ONO stacked layer.
3Adaptability or versatility
If dual-thickness gate oxides are formed for different device regions, then both high voltage devices and logic/analog devices can be integrated, but the conventional method requires forming a top SiOx layer that is subsequently altered by cleaning and oxidizing processes
Solution Approach 1:
The invention achieves dual-thickness gate oxides by segmenting the formation process into two separate gate oxide layers formed at different stages, eliminating the need for a top SiOx layer that would compromise SONOS memory device performance.
Solution Approach 2:
The first gate oxide layer for high voltage devices is formed preliminarily before other processing steps, ensuring its thickness is established and protected from subsequent cleaning and oxidizing processes that would alter it.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the yield and performance of semiconductor ICs by maintaining the thickness and processing window of the ONO structure, ensuring optimal electric performance for both SONOS memory and logic/analog devices.
Implementation Method 1
a first gate oxide layer is formed on a substrate covering on a high voltage region, a memory region and a logic/analog region
Implementation Method 2
the effects of cleaning and oxidizing can dramatically alter the thickness of the top SiOx layer
Data Source
AI summary
A method for fabricating a semiconductor integrated circuit (IC) having a SONOS memory device and a logic/analog device requiring different gate oxide layers comprises steps as follows: A substrate having a high voltage region, a memory region and a logic/analog is firstly provided. Next, a first gate oxide layer is formed on the high voltage region, the memory region and the logic/analog. The first gate oxide layer is then patterned to expose the logic/analog region and to define a first channel area and a second channel area respectively on the memory region and the high voltage region. Subsequently, a silicon oxide-silicon nitride-silicon oxide (ONO) structure is formed on the first channel area. A second gate oxide layer is then formed on the logic/analog and patterned to define a third channel area.