3D NAND Metal Via Formation via Segmented Etching
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Solution Overview
Problem
During the fabrication of 3D NAND devices, etching damages can occur, affecting the performance by mismatching the contact between metal vias and control gates, leading to inconsistent contact performances across different layers.
Innovation Solution
A method involving the formation of a staircase-stacked control gate structure with sequentially recessed second ends, followed by a series of etching processes to create through holes and metal vias, ensuring precise alignment and reduced damage by synchronizing the etching of all layers simultaneously.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional etching processes are used to form metal vias in 3D NAND devices, then the fabrication process is simpler, but etching damages occur causing mismatch between metal vias and control gates
Solution Approach 1:
The etching process is segmented into multiple sequential steps: forming openings in hard mask layer, forming holes in dielectric layer, and forming through holes to expose control gate surfaces. Each step uses specific etching conditions optimized for that layer, preventing damage to control gates while achieving precise alignment.
Solution Approach 2:
The hard mask layer is formed and patterned with openings in advance before etching the dielectric layer. This preliminary patterning ensures that subsequent etching steps are precisely guided, preventing misalignment between metal vias and control gates while reducing etching damage through controlled material removal.
2Reliability
If etching is performed to create metal vias, then electrical connection is established, but etching damages adversely affect device performance
Solution Approach 1:
The hard mask layer serves as an intermediary protective layer during the etching process. It is patterned with openings that guide the etching of the dielectric layer while protecting the control gate structure from direct etching damage, ensuring clean interfaces and reliable electrical contacts.
Solution Approach 2:
The patent replaces aggressive mechanical etching that causes damage with a more controlled chemical etching process through holes in the dielectric layer. This substitution allows precise formation of metal via contact holes without adversely affecting the control gate structure, improving contact quality and device reliability.
3Reliability
If metal vias are formed to connect control gate layers, then electrical connectivity is achieved, but inconsistent contact performance occurs across different layers
Solution Approach 1:
The via formation process is segmented into distinct steps for each control gate layer, with each layer's metal via formed through its own sequence of opening formation, hole etching, and through-hole creation. This segmented approach ensures consistent contact performance across all layers by applying the same precise process to each.
Solution Approach 2:
The etching parameters are optimized and adjusted for each specific dielectric layer and control gate interface. By changing etching conditions (chemistry, power, gas flow) to match the specific requirements of each layer, consistent via formation accuracy and contact performance are achieved across all control gate layers.
Data Source
AI summary
A method for forming a 3D NAND structure includes providing a semiconductor substrate; forming a control gate structure having a plurality of staircase-stacked layers, each layer has a first end and a second end; forming a dielectric layer covering the semiconductor substrate, and the control gate structure; forming a hard mask layer on the dielectric layer; patterning the hard mask layer to form a plurality of openings above corresponding second ends of the layers of the control gate structure; forming a photoresist layer on the hard mask layer; repeating a photoresist trimming process and a first etching process to sequentially expose the openings, and to form a plurality of holes with predetermined depths in the dielectric layer; performing a second etching process to etch the plurality of holes until surfaces of the second ends are exposed to form through holes; and forming metal vias in the through holes.