3D Microelectronic Circuit Layout for Dense Analog-Digital Integration
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Solution Overview
Problem
Current 3D microelectronic circuits face limitations in achieving high-density interconnections and optimal performance distribution between digital and analogue components due to large interconnection dimensions and temperature constraints in existing 3D parallel and sequential integration techniques.
Innovation Solution
A microelectronic circuit architecture with a stack of at least three semiconductor layers, where the intermediate layer facilitates high-density interconnections and allows for optimal placement of digital and analogue components, enabling independent optimization of each tier's performance without temperature restrictions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If 3D parallel integration is used to stack multiple 2D circuits, then the proximity between superimposed circuits improves performance by reducing interconnection lengths, but the interconnection dimensions become too large to achieve high-density interconnections
Solution Approach 1:
The patent transitions from 2D planar interconnections to 3D vertical interconnections by stacking multiple 2D circuits in the thickness direction. This dimensional change enables high-density interconnections through the use of TSVs (Through-Silicon Vias) that traverse the substrate vertically, achieving both short connection lengths and high interconnection density simultaneously.
Solution Approach 2:
The patent introduces TSVs as intermediary structures that facilitate electrical connections between stacked 2D circuits. These TSVs act as vertical conduits that penetrate the substrate, enabling compact and dense interconnections between different circuit layers while maintaining signal integrity and reducing parasitic effects.
2Ease of manufacture
If digital and analogue functions are integrated in the same semiconductor layer, then monolithic integration is achieved, but performance optimization is limited due to conflicting requirements between digital and analogue components
Solution Approach 1:
The patent segments the microelectronic circuit into multiple functional tiers: analogue circuit tier, digital circuit tier, and sensor tier. This vertical segmentation allows each tier to be independently optimized for its specific function while maintaining compact integration. The analogue tier can be designed for low noise and high precision, the digital tier for high speed and low power, and the sensor tier for optimal detection performance.
Solution Approach 2:
The patent resolves the conflict between digital and analogue integration by transitioning from horizontal co-integration to vertical stacking. This enables spatial separation of digital and analogue functions in the thickness direction, allowing independent optimization of each function while maintaining compact form factor and reducing interference between digital and analogue signals.
3Device complexity
If 3D sequential integration is used to create stacked circuits, then high-density interconnections are achieved, but temperature constraints limit the optimization of digital component performance
Solution Approach 1:
The patent employs preliminary action by forming TSVs and performing low-temperature processing steps before fabricating the digital circuit tier. This allows the digital components to be manufactured on a pre-prepared substrate with existing interconnection structures, enabling optimal processing conditions for digital devices without being constrained by subsequent high-temperature steps.
Solution Approach 2:
The patent segments the manufacturing process into temperature-staged tiers: the sensor and analogue tiers are fabricated first at higher temperatures, then the digital tier is added subsequently at lower temperatures. This temporal and spatial segmentation of manufacturing processes allows each tier to be optimized for its specific temperature requirements while maintaining overall integration.
Data Source
AI summary
A microelectronic circuit comprising:a stack of lower, intermediate and upper circuit tiers,a matrix of devices outputting and/or receiving analogue electrical signals, made in the upper circuit tier,an analogue amplification and/or processing circuit made in the lower circuit tier,a digital processing circuit made in the intermediate circuit tier,an analogue-to-digital and/or digital-to-analogue conversion circuit made in the lower and/or intermediate circuit tier, electrically coupled to the analogue circuit and the digital circuit,electrical interconnections passing through the intermediate circuit tier and coupling the analogue circuit to the devices.