Solid-State Devices TRIZ Cases

Inorganic emitters and quantum-dot conversion at tiled display edges improve visibility and image quality while limiting process cost.

A planarization adhesive layer enables precise microdevice-to-backplane alignment and durable electrical bonding despite surface non-uniformities.

A stacked control electrode and insulating layers boost electron injection and pixel density, improving OLED brightness and resolution.

Stacked wider-bandgap semiconductor layers suppress pixel crosstalk and dark current while preserving full photoelectric conversion sensitivity.

Low-index patterns and a high-index layer cut interface reflection, improving image sensor light use and quantum efficiency.

Magnetic pickup with a glass interface speeds micro-LED chip transfer while reducing chip damage and wear on the manufacturing apparatus.

A wide-upper, narrow-lower DTI trench pushes the air gap deeper to cut leakage, avoid cracking, and improve breakdown voltage.

Segmented cell via contacts link dummy storage patterns to improve MTJ alignment, electrical connectivity, and fabrication yield.

A single bendable substrate routes front-to-rear display wiring to prevent side wire disconnection and simplify micro LED module manufacturing.

Multi-layer connection lines around light-transmitting areas cut frame width while reducing capacitance and signal crosstalk.

Simultaneous transfer of heat-activated downconverter layers improves micro-LED phosphor alignment, bonding strength, and throughput.

An organic insulating layer smooths alignment electrode height differences to prevent shorts and improve light emitting element reliability.

A fully converting wavelength layer keeps unconverted pump light below 10%, enabling segmented LEDs to maintain precise color without crosstalk.

Dummy polysilicon in a FinFET is reused as a resistor to shrink ESD and filter circuit area while maintaining high resistance.

Virtual grid lines enable non-integral standard cell heights, reducing IC die size while preserving routing flexibility and performance.

NbTiN high kinetic inductance wires link Josephson junctions and capacitors to cut parasitic coupling and support denser SFQ circuits.

A dual-gate transistor combines light sensing and switching to shrink module area and raise display panel aperture ratio.

Cross-bar MFM capacitor arrays with precise metal contacts reduce switching current noise, enabling accurate small-area ferroelectric characterization.

Protective layers and split contact holes let HF lower silicon contact resistance without damaging oxide-semiconductor connections.

Rolling members engage edge holes to keep the OLED base taut during deposition, limiting warpage, vibration, contamination, and layer variation.

Segmented active-layer routing overlaps data lines to enlarge TFT drain contact area, cutting resistance and improving microdisplay response.

A three-tier 3D circuit uses an intermediate layer to densify interconnects while separating analog and digital functions for low noise and high speed.

A stacked RGB LED with a floating reflection layer improves white light mixing, sub-pixel area efficiency, and display mounting yield.

Opposite-type guard rings and a U-shaped programmable cell structure improve electrostatic discharge handling in scaled semiconductor layouts.

A tunnel oxide film blocks oxygen loss in the oxide semiconductor layer, stabilizing charge transfer and improving image quality with lower noise.

A three-layer doped interface stack helps thin dielectric capacitors maintain high capacitance while suppressing leakage current.

A body ring beneath the gate-source ESD diode redistributes electric fields to reduce leakage and sustain breakdown voltage in power MOSFETs.

A penetrating dual-layer pad structure limits tungsten exposure and smooths silicon-tungsten steps to improve image sensor reliability.

An outer-capping electrode and passivation layout enable physical-contact connection and easier repair in high-resolution displays.

Clamping grooves and a barrier layer enable precise, high-rate LED transfer without laser irradiation, reducing cost and avoiding performance degradation.

A low-resistance contact structure and gate extensions cut channel resistance while preserving positive transition voltage and read switching.

A buried connection tower links the I/O pad, functional circuitry, and ESD clamp to lower discharge resistance and protect miniaturized ICs.

Fluidic self-assembly transfers small elements from dissimilar substrates onto one base, improving spacing control and transfer productivity.

Dummy cells around a memory array shield edge cells from etching and polishing variation, improving yield and read/write stability.

A planar Fresnel structure above the photodiode focuses photons near the p-n junction, boosting signal amplitude without lens-heavy IC fabrication.

Different embedded electrode depths suppress noise and dark current in photoelectric conversion pixels while preserving charge transfer and miniaturization.

Oblique light-splitting structures and segmented pixel islands enable bidirectional naked-eye 3D viewing while maintaining resolution and reducing crosstalk.

A silicon-germanium dual-level sensor separates visible and NIR/SWIR detection to improve quantum efficiency, color fidelity, and depth sensing.

An asymmetric mesa, reflective sidewall layer, and ion implantation region improve μ-LED current confinement, light extraction, and emission uniformity.

Regularly spaced nanoscale holes over photodiodes refract visible light to raise blue-green quantum efficiency in CMOS pixel arrays.

A hybrid TFT layout uses oxide transistors in the display area and polysilicon at the periphery to improve speed, uniformity, and fabrication simplicity.

Redundant same-color sub-pixels and shared electrodes let defective display emitters be replaced more easily with less wiring complexity.

A multi-stage lock cylinder linkage prevents edge loosening in LED screens, improving frame alignment and locking stability.

A low-resistivity conductive structure around pixel electrodes diverts interfering charges without extra insulating layers, improving display stability.

A reflective functional layer makes micro-LED transfer misalignment visible early, reducing contact defects and rework time on TFT substrates.

A diagonal micro LED pad layout with molded backplane pads increases mounting margin and supports self-alignment in dense LED bonding.

Through-holes in micro LED mounting electrodes let laser energy reach the bond interface, strengthening metal joining and reducing point defects.

A buried-trench current channel boosts source-follower width in scaled image sensor pixels, improving noise performance without shrinking photodiodes.

Placing the polarization switching structure on the FinFET gate enables smaller pads, flexible area tuning, and higher anneal temperatures.

Plasma irradiation reshapes recessed optical member surfaces to tune wavelength-dependent transmittance and improve light diffusion uniformity.

A stacked SPAD and visible-light pixel array separates circuits onto a bonded substrate to shrink pixels and align image and distance sensing.

A Cr3+-doped monoclinic phosphor converts blue or near-UV LED light into broad-band NIR with better efficiency and thermal stability.

Roughening the SOI isolation trench bottom to 2-6 nm helps suppress crosstalk and parasitic currents while enabling RF and digital co-integration.

Varying wire density in the trace layer cuts LED display stray light by at least 30% while preserving conductivity, transparency, and image quality.

A shared-plate stack of ferroelectric and paraelectric capacitors raises capacitance density without adding proportional stack complexity.

A thin wiring copper layer plus a thicker elevated drive lead cuts substrate stress, prevents warping, and still carries Mini LED current loads.

A stacked sensing and processing die package uses a dam structure, light-transmitting sheet, and conductive connectors to improve compact optical integration.

Specific hole-transport and emitting compounds cut OLED drive voltage while improving current efficiency, quantum efficiency, and lifespan.

Mixed high-fin and low-fin rows raise drive current where needed while limiting power use and silicon area in integrated circuit cells.

A light-absorbing layer trims broad InP QLED emission tails to widen color gamut and improve color purity with limited efficiency loss.

Light-blocking walls and a patterned film suppress stray light in imaging pixels, reducing crosstalk while preserving on-chip lens collection.

A bidirectional diode coupling circuit and series resistor improve ESD resistance across multiple power supplies while preserving signal transmission.

Gap-filling conforming layers flatten color filter arrays, limiting microlens focal shifts, cross-talk, and light loss in CMOS imagers.

An organic resin filter over adjacent pixels blocks visible light while keeping infrared transmission stable across incident angles for better detection accuracy.

Non-overlapping backplane wire end surfaces let cutting lines intersect one wiring type at a time, reducing short-circuit risk and yield loss.

Sequential mask exposure and etching form sharp active corners and straight end caps to reduce rounding, pattern growth, and electrical shorts.

Rounded connecting electrodes and a stepped insulating layer suppress sidewall formation during etching, lowering short-circuit risk in displays.

A recess around inter-substrate connection sections compensates height variation, improving bonding consistency in stacked imaging elements.

Compound semiconductor heteroepitaxy on silicon extends photodetector wavelength range and sensitivity while staying compatible with CMOS manufacturing.

Localized aluminum diffusion at chip side facets raises the active-zone band gap to reduce catastrophic optical damage and improve emission efficiency.

By integrating driving chips and the light emitting layer on one substrate, this case cuts chip cost and enables smaller LED display packages.

Parallel channel regions using different oxide semiconductors raise TFT current output and reliability in display panels.

Uneven planarization patterns and disconnected reflective electrodes improve viewing angle, color capability, and display uniformity at lower cost.

Quarter-wave phase-shifting layers aligned with microlenses suppress diffraction-driven petal flare and improve image sensor quality.

A conductive layer over circuit lines dissipates LED heat and reflects light, improving backlight reliability and efficiency.

Spare light-emitting elements are selectively disabled to offset chip mounting deviation and keep printing points uniformly exposed.

A silicon nitride spacer surrounds MIM capacitor sidewalls to block moisture and plasma damage while a recessed upper electrode helps prevent shorting.

Boron-containing polycyclic compounds tune OLED organic layers to raise luminous efficiency and extend device lifetime without overly complex structures.

Segmented insulation layers and sidewall protrusions protect micro LED chips during transfer, preventing cracking, leakage, and efficiency loss.

A plasma nitride barrier in an SOI stack improves bond interface purity, layer uniformity, and transfer efficiency while reducing waste and cost.

Frame-region signal lines form capacitors with low-load gate lines to equalize delay across special-shaped display substrates.

Differently positioned dielectric layers let adjacent capacitors pack more densely while preserving operational reliability in semiconductor structures.

A cover plate with a light shielding layer lets neighboring display panels abut cleanly, reducing wire breakage and chromatic aberration.

Varying dielectric layer thickness with reflective and anti-reflective layers improves image sensor light transmittance and resolution.

Diagonal and horizontal microlens gaps suppress petal flare from reflected light while preserving sensitivity in high-definition imaging.

Embedded dark pixel sensors enable per-pixel dark current calibration in CMOS arrays, reducing hot pixels and image noise.

Shallow trench isolation textures extend the optical path in thin silicon imagers, improving longer-wavelength absorption without thicker layers.

An electrode segment extended to the sidewall enables electroplating, boosting light intensity, lowering forward voltage, and reinforcing the LED.

Stacked insulating layers with differently sized openings ease electrode spacing limits, enabling smaller pixels with lower dark current and noise.

A channeled ferromagnetic magnet structure cuts back-bias cost and helps stabilize magnetic sensor performance during overmold packaging.

Vertical LED stacks with bonding layers and buried vias increase sub-pixel area, support higher pixel density, and shorten mounting time.

Etched trenches and plateaus near a buried p-n junction cut optical and electrical crosstalk while avoiding complex high-field passivation.

A current limiting path tied to LDMOS isolation regions suppresses parasitic SCR turn-on under light loads and expands SOA.

Secondary shallow N-type doping cuts fin resistance in FinFET varactors, improving RF quality factor while preserving capacitance tunability.

A convex or concave dielectric layer expands P-N junction area to raise photoelectric current and quantum efficiency in CMOS image sensors.

Boundary-region cuts in an OLED touch mesh improve sensitivity and lower resistance while reducing visible cuts and mura defects.

Separate deposition of lower and upper insulating sub-layers preserves interface characteristics and reduces defect-driven short circuits.

Pre-formed divided phosphor structures transfer onto LED sub-pixels to avoid partition walls, improving color separation and high-resolution display yield.

A conductive shielding layer between electrode lines suppresses coupling noise and preamplifier oscillation in high-pixel detector arrays.

Embedded metal particles in a MOF layer regulate conductive filament density and distribution for more uniform set/reset voltages and endurance.

A ring-shaped PCM heater cuts contact area to lower RESET current, improve Joule heating efficiency, and reduce power dissipation.

A dummy electrode blocks particle intrusion into pixel electrodes, reducing galvanic dark spots and short circuits in display panels.

Selective phosphor placement around LED chips removes internal dams, freeing more emitting area while keeping white light uniform.

Overlapping touch-sensing and driving lines across organic and inorganic dielectric films simplifies OLED touch integration and prevents spot defects.

Two blue LEDs and Ce-activated aluminate plus red phosphors broaden the spectrum to improve R9-R15 color rendering and sunlight-like visibility.

Laser ablation clears metal from the camera sensing region to raise transmittance and image quality without degrading the main display.

A single photoelectric region with switched image and event readout improves pixel isolation, image quality, and dynamic vision sensing.

Color-specific surface level control and planarization keep RGB organic layers uniform, preserving OLED emission reproducibility and stability.

Vertical RGB LED stacks with buried connections expand sub-pixel area in dense displays while cutting mounting time and improving yield.

A rigid reinforcement member joined with a lower-rigidity sealing layer suppresses LED substrate warping while reducing separate assembly steps.

A closed magnetic path and stacked isolation barriers enable compact PCB transformers to deliver reinforced galvanic isolation with lower flux leakage.

Rail-over-active standard cell layout lowers power resistance while preserving speed and manufacturable IC scaling.

A protrusion-based microstructure layer and lower-index planarization layer cut OLED panel reflectivity, boosting brightness without extra power.

A spaced vertical transfer gate and p-type barrier cut floating diffusion capacitance, enabling higher conversion gain and precise low-charge sensing.

Multiple stacked processor-DRAM units use reconfigurable ring links and handshake signaling to run parallel ML tasks with scalable data exchange.

A coupling capacitor and switched charge-sense path let self-capacitance touch sensors use high-voltage charging to improve SNR without overstressing the IC.

A widened light modulator over pixel isolation blocks light from polysilicon, reducing optical loss, blooming, and autofocus blur.

A composite insulating film with an elastic member guides even crack propagation during separation, reducing height differences and improving electrode contact.

Varying the intermediate dielectric layer across pixel regions tunes microcavity length, narrows FWHM, and improves OLED color uniformity.

Alternating local bit and source lines with separate odd and even word lines cut resistance paths and increase 3D memory cell density.

Alignment-marked insulating layers help minimize through holes in tiled displays, reducing visible seams, defects, and production cost.

A single source-follower handles global dump and readout to shrink pixel area, cut power, and preserve low-noise imaging.

LED self-heating selectively cures adhesive to bond aligned phosphor pixels, improving RGB microLED accuracy, density, and yield.

A GeSi absorption layer and dual phase-switched carrier collection raise photodiode speed, SNR, and depth resolution in ToF sensing.

Separated insulation openings and mesa indent regions lengthen solder paths, protecting the ohmic reflection layer and LED reliability.

Decoupling memory-array and control-logic processing enables stacked 3D NAND and resistance memory with higher density and lower cost.

Charge-trap memory materials and interfacial dipoles curb lateral charge migration in dense 3D NAND, improving retention and low-voltage operation.

A two-step channel fill raises the merging point in 3D NAND, reducing channel breakage risk and improving BSG electrode control.

Integrating touch electrodes, TFTs, and mini/micro-LEDs on one substrate enables active three-color display while improving panel manufacturing efficiency.

A segmented, non-flat transfer substrate places nanorod LEDs accurately at high density while simplifying transfer and tolerating pixel defects.

Frequency-response-guided pad sizing, pitch, and overlap tuning reduces interference and improves signal transmission between 3D stacked chips.

Selective sidewall etching lowers indium at LED trench edges, widens the bandgap, and cuts parasitic recombination in small LEDs.

A quad sub-pixel layout cuts micro-LED transfer count and pixel gaps, enabling higher-resolution displays with lower integration complexity.

A block copolymer auxiliary layer improves perovskite film uniformity and crystallinity while preserving charge transport for higher luminance.

A front-side hollow region and back-side insulating solid around a through conductor reduce thermal stress while preserving semiconductor strength.

Helium or argon plasma breaks carbon-oxygen bonds in acryl insulating layers, cutting outgassing and improving display reliability.

Software-based EP signal processing cuts noise while preserving low-amplitude cardiac signal integrity for clearer mapping and catheter positioning.

A step-adjusting layer and modular unit pixel layout let tiny micro LEDs mount reliably on circuit boards without sacrificing display density.

A fin-cut isolation region in a FinFET ESD structure enables compact static discharge protection with low turn-on voltage and low on-resistance.

Tuned HOMO, LUMO, and triplet energy levels improve charge injection, confine excitons, and extend blue OLED display lifespan.

An In-Ga-Sn-Zn oxide layer between the electrode and photoelectric layer improves charge transfer, lowers noise, and enhances image quality.

A low-modulus protective layer seals light-emitting units against moisture and air while limiting thermal-stress peeling in display panels.

Contact electrodes and insulating patterns stabilize light emitting elements while cutting mask count and simplifying pixel fabrication.

A layered pad-contact bridge layout keeps rework access while shielding wiring from impurity-driven corrosion in display panels.

Radiation shields placed between detector substrates attenuate stray radiation, protecting electronics and preserving scan accuracy.

A valley-shaped peripheral barrier and multilayer encapsulation block moisture and gas ingress, preserving OLED image quality and durability.

Transparent tunnel junctions replace absorbing p-GaN and metal mirrors, enabling top and bottom UV emission with higher light extraction.

Planar position code patterns placed between subpixels enable precise pen coordinate detection without adding separate display fabrication steps.

Optimized energy levels in the organic electroluminescent device reduce operating voltage and extend service life by preventing carrier trapping.

Merging touch sensing electrodes into OLED electrode layers via universality principles to remove bonding processes and reduce overall thickness.

A mixed valence oxide memory element layers metals with distinct Gibbs free energies to supply oxygen atoms under bias voltage.

UV LED array operates directly on alternating current using opposing polarity connections, eliminating rectifier complexity.

A non-linear diode in amorphous silicon RRAM switches resistance states while blocking unwanted current paths.

A flip-chip light emitting diode spaces connectors laterally from bump pads to ensure reliable electrical connections.

Measurement system uses shaped reflector and mirrors to create multiple angles of arrival for antenna testing.

An on-chip optofluidic microscope integrates plasmonic lenses with microfluidic channels and CMOS sensors to generate 4D images via computational photography.

Replacing expensive spiro-OMeTAD with a soluble butadiene compound lowers synthesis costs while maintaining high photoelectric conversion efficiency.

Removing color filters from the white sub-pixel prevents debris contamination that reduces light transmissivity and brightness in flat panel displays.

Segmented interconnect layers with extended connection parts reduce contact resistance in cross-point memory devices, improving operation stability.

Stacked word lines and vertical channels increase integration density without requiring fine lateral patterning, reducing equipment costs.

Alternating bias direction in a self-heating circuit mitigates tungsten migration and dielectric breakdown risks during program erase cycles.

Ion separation creates a heterogeneous phase-change material layer that reduces power consumption while maintaining reliability.

A fluoride fluorescent material doped with tetravalent manganese ions produces high-intensity red light emission.

Cu-Ni-Sn sinter pastes form void-free intermetallic joints through transient liquid phase diffusion at low processing temperatures.

A display device integrates an input-sensing unit with a sensing electrode directly on an anti-reflection unit.

Integrated PCB heating and cooling components stabilize MEMS sensors against environmental temperature drift, ensuring accurate antenna monitoring readings.

An etch-stop layer protects the substrate during vertical channel formation, enabling higher integration density without reliability degradation.

Holographic optical elements guide image lights through a light guide unit to produce clear three-dimensional images without polarized glasses.

Isolated projections on tray back surfaces disrupt electrostatic fields to prevent semiconductor chip adhesion during stacked transport operations.

Segmented pixel arrays on flexible substrates resolve strain-induced nonuniform background signals to achieve high-resolution spatial mapping.

Alternating gate and Schottky electrodes in a deep trench adjust area ratios to prevent local current concentration and enhance breakdown voltage.

Edge-to-edge substrate arrays with encapsulation alignment structures resolve manufacturing precision constraints to enhance light detection resolution.

An integrated island structure with a pnpn-type light-emitting thyristor eliminates bonding pads, reducing chip size and manufacturing costs.

Array substrate design places data lines at sub-pixel edges to reduce electric-field-free regions.

A stacked-layer light-emitting element uses an exciplex to transfer energy between organic compounds, resolving inefficient host-to-guest transfer.

A hole transporting layer uses materials with specific HOMO and LUMO energy levels to optimize charge injection in organic light emitting devices.

An ytterbium interlayer lowers the energy barrier at the cathode-electron transport layer interface, reducing operating voltage and extending device lifetime.

A planar single-crystal phase change memory device uses asymmetric contacts and current pulses to form amorphous regions within a crystalline matrix.

A segmented LED die structure enables independent color control through electrophoretic phosphor deposition on discrete junctions.

A novel polymer structure enhances electron transport and triplet energy in organic light-emitting devices.

Stacked insulating and polycrystalline silicon layers form vertical channels through selective trench etching and silicidation.

A stacked structure joins an aluminum nitride ferroelectric layer with a magnesium oxide tunnel barrier.

A carbon nanotube film serves as a sacrificial mask during epitaxial growth, enabling precise groove formation without complex lithography or etching.

A diamond-like carbon-nitride-carbon hardmask layer incorporates nitride atoms to form stable sp3 bonds.

A protective organic layer on the black matrix absorbs laser energy during repair processes to maintain structural integrity.

Segmented guide films absorb impact energy at rounded corners without damaging the protective layer during flexible manufacturing processes.

Integrates gate lines, gate electrodes, and common electrode into a single photolithographic layer for FFS LCD array substrates.

An integrated circuit merges a Hall probe with a coil to detect magnetic fields across a broad frequency range.

Simultaneous capacitor and resistor formation in integrated circuits reduces fabrication cycle time and cost by merging separate process flows.

Cavity capacitors buffer electrostatic discharge within the LED chip, minimizing light absorption by electrodes to increase extraction efficiency.

A thin film encapsulation structure uses an intermediate buffer layer to stabilize atomic layer deposition films on display substrates.

A linear accelerator adjusts focal spot size and filter positions to optimize radiation beam characteristics for imaging.

Segmented polygon heads rotate to parallelize micro LED die pickup, resolving manufacturing scalability limits for sub-pixel display arrays.

Substrate biasing during HDP-CVD silicon nitride deposition tunes film stress to improve barrier properties.

Segmented auxiliary electrodes remove residual layers while protecting bank hydrophobicity to enhance light emission efficiency.

A grooved substrate structure houses the organic light emitting element and sealant within recessed areas to form a compact display assembly.

An inclined adhesive-layer-accommodating portion contains the bonding layer, reducing deep ultraviolet-induced discoloration and improving luminous efficacy.