Solid-State Devices TRIZ Cases

Inorganic emitters and quantum-dot conversion at tiled display edges improve visibility and image quality while limiting process cost.

A planarization adhesive layer enables precise microdevice-to-backplane alignment and durable electrical bonding despite surface non-uniformities.

A stacked control electrode and insulating layers boost electron injection and pixel density, improving OLED brightness and resolution.

Stacked wider-bandgap semiconductor layers suppress pixel crosstalk and dark current while preserving full photoelectric conversion sensitivity.

Low-index patterns and a high-index layer cut interface reflection, improving image sensor light use and quantum efficiency.

Magnetic pickup with a glass interface speeds micro-LED chip transfer while reducing chip damage and wear on the manufacturing apparatus.

A wide-upper, narrow-lower DTI trench pushes the air gap deeper to cut leakage, avoid cracking, and improve breakdown voltage.

Segmented cell via contacts link dummy storage patterns to improve MTJ alignment, electrical connectivity, and fabrication yield.

A single bendable substrate routes front-to-rear display wiring to prevent side wire disconnection and simplify micro LED module manufacturing.

Multi-layer connection lines around light-transmitting areas cut frame width while reducing capacitance and signal crosstalk.

Simultaneous transfer of heat-activated downconverter layers improves micro-LED phosphor alignment, bonding strength, and throughput.

An organic insulating layer smooths alignment electrode height differences to prevent shorts and improve light emitting element reliability.

A fully converting wavelength layer keeps unconverted pump light below 10%, enabling segmented LEDs to maintain precise color without crosstalk.

Dummy polysilicon in a FinFET is reused as a resistor to shrink ESD and filter circuit area while maintaining high resistance.

Virtual grid lines enable non-integral standard cell heights, reducing IC die size while preserving routing flexibility and performance.

NbTiN high kinetic inductance wires link Josephson junctions and capacitors to cut parasitic coupling and support denser SFQ circuits.

A dual-gate transistor combines light sensing and switching to shrink module area and raise display panel aperture ratio.

Cross-bar MFM capacitor arrays with precise metal contacts reduce switching current noise, enabling accurate small-area ferroelectric characterization.

Protective layers and split contact holes let HF lower silicon contact resistance without damaging oxide-semiconductor connections.

Rolling members engage edge holes to keep the OLED base taut during deposition, limiting warpage, vibration, contamination, and layer variation.

Segmented active-layer routing overlaps data lines to enlarge TFT drain contact area, cutting resistance and improving microdisplay response.

A three-tier 3D circuit uses an intermediate layer to densify interconnects while separating analog and digital functions for low noise and high speed.

A stacked RGB LED with a floating reflection layer improves white light mixing, sub-pixel area efficiency, and display mounting yield.

Opposite-type guard rings and a U-shaped programmable cell structure improve electrostatic discharge handling in scaled semiconductor layouts.

A tunnel oxide film blocks oxygen loss in the oxide semiconductor layer, stabilizing charge transfer and improving image quality with lower noise.

A three-layer doped interface stack helps thin dielectric capacitors maintain high capacitance while suppressing leakage current.

A body ring beneath the gate-source ESD diode redistributes electric fields to reduce leakage and sustain breakdown voltage in power MOSFETs.

A penetrating dual-layer pad structure limits tungsten exposure and smooths silicon-tungsten steps to improve image sensor reliability.

An outer-capping electrode and passivation layout enable physical-contact connection and easier repair in high-resolution displays.

Clamping grooves and a barrier layer enable precise, high-rate LED transfer without laser irradiation, reducing cost and avoiding performance degradation.

A low-resistance contact structure and gate extensions cut channel resistance while preserving positive transition voltage and read switching.

A buried connection tower links the I/O pad, functional circuitry, and ESD clamp to lower discharge resistance and protect miniaturized ICs.

Fluidic self-assembly transfers small elements from dissimilar substrates onto one base, improving spacing control and transfer productivity.

Dummy cells around a memory array shield edge cells from etching and polishing variation, improving yield and read/write stability.

A planar Fresnel structure above the photodiode focuses photons near the p-n junction, boosting signal amplitude without lens-heavy IC fabrication.

Different embedded electrode depths suppress noise and dark current in photoelectric conversion pixels while preserving charge transfer and miniaturization.

Oblique light-splitting structures and segmented pixel islands enable bidirectional naked-eye 3D viewing while maintaining resolution and reducing crosstalk.

A silicon-germanium dual-level sensor separates visible and NIR/SWIR detection to improve quantum efficiency, color fidelity, and depth sensing.

An asymmetric mesa, reflective sidewall layer, and ion implantation region improve μ-LED current confinement, light extraction, and emission uniformity.

Regularly spaced nanoscale holes over photodiodes refract visible light to raise blue-green quantum efficiency in CMOS pixel arrays.

A hybrid TFT layout uses oxide transistors in the display area and polysilicon at the periphery to improve speed, uniformity, and fabrication simplicity.

Redundant same-color sub-pixels and shared electrodes let defective display emitters be replaced more easily with less wiring complexity.

A multi-stage lock cylinder linkage prevents edge loosening in LED screens, improving frame alignment and locking stability.

A low-resistivity conductive structure around pixel electrodes diverts interfering charges without extra insulating layers, improving display stability.

A reflective functional layer makes micro-LED transfer misalignment visible early, reducing contact defects and rework time on TFT substrates.

A diagonal micro LED pad layout with molded backplane pads increases mounting margin and supports self-alignment in dense LED bonding.

Through-holes in micro LED mounting electrodes let laser energy reach the bond interface, strengthening metal joining and reducing point defects.

A buried-trench current channel boosts source-follower width in scaled image sensor pixels, improving noise performance without shrinking photodiodes.

Placing the polarization switching structure on the FinFET gate enables smaller pads, flexible area tuning, and higher anneal temperatures.