3D P-N Junction Semiconductor Structure for Higher Image Sensor Sensitivity

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Solution Overview

Problem

Conventional CMOS image sensors face limitations in increasing the current generated by the photosensitive elements, which affects their sensitivity and efficiency in light detection.

Innovation Solution

The semiconductor device incorporates a dielectric layer with convexities or concavities, allowing the semiconductor substrate's semiconductor layers to have increased surface area contact, thereby enhancing the current generated by the photosensitive elements or photoelectric conversion structures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the pixel photosensitive region size is increased to improve light sensing sensitivity, then the sensitivity is improved, but the device area and complexity increase

Engineering Contradiction:
Improvelight sensing sensitivityVSAvoidpixel area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent transitions from a planar P-N junction to a three-dimensional vertically stacked P-N junction structure. Multiple semiconductor layers (first type and second type alternating) are stacked vertically to form multiple P-N junctions in the depth direction, increasing the effective junction area without expanding the lateral pixel footprint.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements nested semiconductor layers where first type and second type semiconductor layers are alternately stacked, with each layer containing P-N junctions. The structures are nested vertically, with metal circuits and capacitors integrated within the stacked semiconductor layers, maximizing space utilization within the pixel volume.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Power

If conventional planar P-N junction structure is used, then the device structure is simple, but the current generation capability is limited

Engineering Contradiction:
Improvecurrent generation capabilityVSAvoidstructure complexity
Core Design Contradiction:
PowerVSDevice complexity

Solution Approach 1:

The patent creates multiple P-N junctions in the vertical dimension by stacking semiconductor layers, transforming a single planar junction into multiple three-dimensional junctions. This increases the total junction surface area and current generation capability without significantly complicating the manufacturing process.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent employs curved or inclined side surfaces in the semiconductor layers and metal circuits, replacing traditional planar structures. The curved surfaces increase the junction area between semiconductor layers and improve light trapping efficiency while maintaining manufacturability through standard semiconductor processing techniques.

Inventive Principle:
Principle #14Spheroidality (Curvature)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration increases the surface area of the P-N junction, leading to higher drift current and quantum efficiency, thus improving the sensitivity and efficiency of the image sensor.

Implementation Method 1

the current generated by the irradiation of the photosensitive element or the photoelectric conversion structure in the semiconductor substrate can be increased

Methodology Applied
Scientific EffectPhotoelectric conversion: Photoelectric Effect

Data Source

PatentUS11961854B2Semiconductor device
Publication Date: 2024.04.16 LEE SYWE NENG
  • US11961854B2 patent drawing
  • US11961854B2 patent drawing
  • US11961854B2 patent drawing

AI summary

A semiconductor device, including a dielectric layer and a semiconductor substrate, is provided. The dielectric layer has a convexity or a concavity. The semiconductor substrate includes a first type semiconductor layer and a second type semiconductor layer sequentially stacked on the dielectric layer. The first type semiconductor layer is disposed on the convexity or the concavity. A top surface and a bottom surface of the first type semiconductor layer are protruded according to the convexity or recessed according to the concavity. A bottom surface of the second type semiconductor layer is protruded according to the convexity or recessed according to the concavity.