Layered Cross-Point Memory Device Contact Resistance Reduction
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving stable operation due to high contact resistance between interconnect layers, which affects the reliability and efficiency of memory storage.
Innovation Solution
The semiconductor memory device incorporates a specific layered structure with a first and second interconnect layer, a resistance change layer, and a conductive connection part, where the second interconnect layer extends in a third direction crossing the first and second directions, and a second extended connection part is electrically connected to the second core part, reducing contact resistance through strategically placed surrounding regions and extended regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional cross-point structure with simple interconnect layers is used, then the device structure is simple and easy to manufacture, but high contact resistance occurs between interconnect layers affecting operation stability
Solution Approach 1:
The interconnect structure is segmented into multiple functional regions: core parts for signal transmission, surrounding regions for lateral connection, and extended regions for vertical connection. This segmentation allows each region to be optimized for its specific function, reducing overall contact resistance while maintaining manufacturability through standardized fabrication processes
Solution Approach 2:
The patent transitions from conventional two-dimensional planar interconnects to a three-dimensional layered structure with extended regions that protrude vertically. This dimensional change enables direct vertical connections between layers, eliminating the need for complex via structures and reducing contact resistance at layer interfaces
2Reliability
If interconnect layers are directly connected without extended regions, then the manufacturing process is simpler, but contact resistance increases and current flow is restricted
Solution Approach 1:
The extended regions are formed in advance during the interconnect fabrication process, protruding from the insulating layer before final assembly. This preliminary action ensures proper alignment and reduces contact resistance by pre-establishing the connection geometry, while the extended regions can be formed using standard deposition and etching techniques
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes first and second interconnect parts, and a second interconnect connection part. The first interconnect part includes a first core part, and a first interconnect layer. The first interconnect layer includes a first surrounding region and a first extended region. The second interconnect part includes a second core part, and a second interconnect layer. The second interconnect layer includes a second surrounding region and a second extended region. The second extended connection part overlaps a part of the first extended region in the third direction, overlaps the second core part in the first direction, and is electrically connected to the second core part. The second extended surrounding part is provided around the second extended connection part and contains a material contained in the first surrounding region.