Memory Array Edge Cell Layout With Dummy Cells for Etching Robustness
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Solution Overview
Problem
Existing memory array circuits face challenges in sustaining process variations caused by plasma etching or chemical mechanical polishing during fabrication, leading to issues like under-etching or over-etching, which affect the yield and read/write performance of memory cells.
Innovation Solution
The implementation of a memory array circuit design that includes inner and edge memory cells with different physical dimensions and operation conditions, along with the use of dummy cells surrounding the array to prevent etching issues and enhance robustness, by arranging dummy cells inoperative to protect operative edge memory cells and maintain symmetry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are arranged in arrays with edge cells at the boundaries, then the memory array can be fully utilized, but the edge memory cells suffer from process variations caused by plasma etching or chemical mechanical polishing
Solution Approach 1:
Dummy memory cells are pre-formed around the perimeter of the memory array before actual memory cells are programmed. These dummy cells are configured to undergo the same fabrication processes (plasma etching, chemical mechanical polishing) as the actual memory cells, thereby pre-absorbing process variations and protecting the edge memory cells from etching errors and dimensional deviations
Solution Approach 2:
The dummy memory cells act as intermediary structures between the fabrication process and the actual memory cells. They are positioned at the edges and corners of the memory array, serving as buffer zones that absorb the harmful effects of plasma etching and chemical mechanical polishing, thereby protecting the actual edge memory cells from process variations
2Reliability
If dummy cells are added around the memory array to protect edge cells, then manufacturing robustness improves, but device complexity increases
Solution Approach 1:
The dummy memory cells are designed with the same structure, dimensions, and configuration as the actual memory cells. They use identical transistor layouts, capacitor structures, and interconnect patterns, making them homogeneous with the real memory cells. This homogeneity allows them to effectively absorb process variations while maintaining simplicity in design and fabrication
Data Source
AI summary
A memory array circuit includes a memory array and a set of dummy cells surrounding the memory array. The first memory array includes a first set of memory cells located in an inner area of the memory array and a second set of memory cells located along an edge of the memory array. Each dummy cell includes one or more active regions and multiple gate structures over the one or more active regions.