Stacked Memory Arrays With Decoupled Control Logic Processing
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Solution Overview
Problem
Microelectronic device designers face challenges in reducing the size and improving the performance of memory devices due to processing conditions and the configuration of control logic devices, which limit the integration density and performance of memory arrays.
Innovation Solution
A method of forming a microelectronic device with a first control logic region and a first memory array region, followed by the formation of a second control logic region and a second memory array region, where the second control logic devices have lower operational voltage requirements and are configured to control both the vertically extending strings of memory cells and resistance variable memory cells, allowing for enhanced performance and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If processing conditions (temperatures, pressures, materials) are optimized for memory array formation, then memory array performance is improved, but control logic device configurations and performance are limited
Solution Approach 1:
The patent divides the device into two separately formed regions: a memory array region formed under specific processing conditions (temperatures, pressures, materials) and a control logic region formed under different processing conditions. This segmentation allows each region to be optimized independently, resolving the contradiction between memory array performance and control logic device adaptability
Solution Approach 2:
The patent applies different processing conditions to different regions of the device. The memory array region receives processing conditions optimized for memory cell formation, while the control logic region receives processing conditions optimized for transistor performance. This local quality approach enables each region to achieve its optimal performance without compromising the other
2Adaptability or versatility
If the quantity, dimensions, and arrangements of control logic devices are increased to improve functionality, then control capabilities are enhanced, but the horizontal footprint and device size increase
Solution Approach 1:
The patent transitions from a planar arrangement of control logic devices to a three-dimensional vertical stack architecture. Multiple control logic devices are stacked vertically above the memory array, allowing enhanced control capabilities without increasing the horizontal footprint. This dimensional change resolves the contradiction between control logic capabilities and device area
3Quantity of substance
If conventional vertical memory array architectures with strings of memory cells are used, then integration density is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts the select device functionality from the vertical memory cell strings and places it in a separate control logic region. This extraction simplifies the memory array structure and manufacturing process while maintaining high integration density through the vertical stacking of memory cells. The select devices in the control logic region can be formed under different processing conditions, reducing manufacturing complexity
Data Source
AI summary
A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a first control logic region comprising first control logic devices, and a first memory array region vertically overlying the first control logic region and comprising an array of vertically extending strings of memory cells. An additional microelectronic device structure comprising a semiconductive material is attached to an upper surface of the microelectronic device structure. A portion of the semiconductive material is removed. A second control logic region is formed over the first memory array region. The second control logic region comprises second control logic devices and a remaining portion of the semiconductive material. A second memory array region is formed over the second control logic region. The second memory array region comprises an array of resistance variable memory cells. Microelectronic devices, memory devices, and electronic systems are also described.