3D Nonvolatile Memory Vertical Channel Etch-Stop Layer
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Solution Overview
Problem
Two-dimensional memory devices face limitations in integration due to increased interference and disturbance as memory cell size is reduced, necessitating a three-dimensional structure to enhance integration efficiency.
Innovation Solution
A three-dimensional nonvolatile memory device is manufactured with vertically protruding channel layers, alternately stacked interlayer insulating and conductive layers, and a slit between them, featuring an etch-stop layer on the substrate to protect the structure during the etching process, allowing for efficient formation of conductive layer patterns and improved integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell size is reduced in 2-D memory devices, then integration density is improved, but interference and disturbance increase causing reliability degradation
Solution Approach 1:
The patent transitions from 2-D planar memory cell arrangement to 3-D vertical structure by stacking multiple conductive layers and interlayer insulating layers alternately, with channel layers extending vertically to penetrate these stacked layers. This dimensional change allows integration density to increase without reducing individual cell size, thereby maintaining reliability while improving integration.
2Quantity of substance
If 3-D structured memory device is implemented, then substrate area utilization is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent divides the memory structure into multiple discrete stacked layers including conductive layers, interlayer insulating layers, and channel layers. Each layer can be formed and processed independently, allowing complex 3-D structures to be manufactured through sequential deposition and etching steps rather than attempting to create the entire structure in one process.
Solution Approach 2:
The etch-stop layer is formed in advance on the substrate surface at the bottom of the slit region before the main etching process. This preliminary action prevents substrate damage during subsequent etching of the channel layers and ensures precise control of the vertical structure formation, simplifying the overall manufacturing process.
3Shape
If etching process is performed to form vertical channel layers, then 3-D structure is achieved, but substrate damage may occur
Solution Approach 1:
The etch-stop layer is deposited on the substrate surface at the bottom of the slit region before the etching process that forms the vertical channel layers. This layer acts as a protective cushion during etching, preventing the etchant from damaging the substrate while still allowing the formation of the desired vertical channel structure that penetrates through the stacked layers.
Data Source
AI summary
A three-dimensional (3-D) nonvolatile memory device includes channel layers protruding perpendicular to a surface of a substrate, interlayer insulating layers and conductive layer patterns alternately formed to surround each of the channel layers, a slit formed between the channel layers, the slit penetrating the interlayer insulating layers and the conductive layer patterns, and an etch-stop layer formed on the surface of the substrate at the bottom of the slit.