Multi-Supply Semiconductor ESD Coupling for MOS Surge Protection
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Solution Overview
Problem
Semiconductor devices with multiple power supply systems face reduced ESD resistance due to the presence of n-channel MOS transistors, which can lead to transistor breakage under surge conditions, especially when noise propagation occurs between different power supply systems.
Innovation Solution
Incorporating a coupling circuit with a bidirectional diode and ESD protection circuits between high-potential and low-potential side power supplies, along with a resistor element or additional ESD protection circuits, to absorb surges and reduce impedance, thereby enhancing ESD resistance without increasing circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If an n-channel MOS transistor is used in the intermediate buffer coupled to different power supply systems, then signal transmission between power supply systems is enabled, but ESD resistance is lowered
Solution Approach 1:
A p-channel MOS transistor is introduced as an intermediary element between the n-channel MOS transistor and the high-potential side power supply. This p-channel transistor acts as a mediator that blocks ESD current paths while allowing normal signal transmission, thereby resolving the contradiction between maintaining signal transmission capability and improving ESD resistance
Solution Approach 2:
The intermediate buffer circuit is segmented into multiple transistor stages (n-channel MOS transistor for signal transmission and p-channel MOS transistor for ESD protection). This segmentation allows each transistor to perform its specific function independently, enabling the circuit to achieve both signal transmission and ESD resistance simultaneously
2Reliability
If ESD protection circuits are added between power supply systems, then ESD resistance is improved, but circuit area increases
Solution Approach 1:
The ESD protection function is merged with the existing intermediate buffer circuit by utilizing the p-channel MOS transistor that is already part of the buffer structure. This merging eliminates the need for separate ESD protection circuits, thereby improving ESD resistance without increasing circuit area
Solution Approach 2:
The p-channel MOS transistor in the intermediate buffer serves dual functions: normal signal transmission between power supply systems and ESD protection. This multi-functionality allows the same circuit element to address both signal integrity and ESD resistance requirements without additional area overhead
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed configuration effectively improves ESD resistance in semiconductor devices with multiple power supply systems, preventing transistor breakage and maintaining high-speed signal transmission while minimizing circuit overhead.
Implementation Method 1
The coupling circuit includes a bidirectional diode and is configured to couple the first low-potential side power supply and the second low-potential side power supply
Implementation Method 2
The first ESD protection circuit is provided between the first high-potential side power supply and the first low-potential side power supply and is configured to absorb an input surge
Implementation Method 3
The first resistor element is inserted in series between the drain of the first transistor and the first high-potential side power supply
Data Source
AI summary
A first ESD protection circuit is provided between a first high-potential side power supply and a first low-potential side power supply of a first power supply system and a second ESD protection circuit is provided between a second high-potential side power supply and a second low-potential side power supply of a second power supply system. A coupling circuit includes a bidirectional diode and couples the first and second low-potential side power supplies. A first transistor is composed of an n-channel MOS transistor, has a drain coupled to the first high-potential side power supply of the first power supply system, and has a back gate coupled to the second low-potential side power supply of the second power supply system. A resistor element is inserted in series between the drain of the first transistor and the first high-potential side power supply.