FFS LCD Array Substrate Single-Layer Gate and Common Electrode Integration

The patent merges the formation of gate lines, gate electrodes, and common electrode into a single photolithographic process. Specifically, a first conductive layer is patterned to form gate lines and gate electrodes, then a second conductive layer is formed and patterned to form the common electrode, both using photolithography. This integration reduces the number of separate photolithographic processes from six to a fewer number, thereby reducing manufacturing complexity and cost while maintaining the required manufacturing precision for the array substrate.

The patent combines multiple electrode formation steps into integrated photolithographic processes. The gate lines and gate electrodes are formed in one photolithography step using a first conductive layer, and the common electrode is formed in another photolithography step using a second conductive layer. This merging of processes reduces the total number of photolithographic steps from six, thereby lowering manufacturing cost while preserving the quality requirements through controlled patterning processes.

The patent applies local quality by making the common electrode transparent in the display area to improve transmittance and aperture ratio, while the gate lines and gate electrodes can be made of opaque conductive materials where transparency is not required. This localized approach to material selection allows the common electrode to be transparent conducting material (such as ITO) only where needed for light transmission, while other electrodes use more cost-effective opaque materials, thereby improving optical performance without uniformly increasing manufacturing complexity across all electrodes.