3D Stacked Semiconductor Memory With Parallel Current Paths
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Solution Overview
Problem
Current 3D stacked semiconductor memories face challenges in increasing cell density due to limitations in the configuration of resistive switching elements and electrode structures, which affect the efficiency of data storage and retrieval operations.
Innovation Solution
The proposed 3D stacked semiconductor memory design incorporates a unique configuration with separate odd and even word lines, alternately arranged local bit and source lines, and a separating film to reduce the resistance path and enhance cell current flow, allowing for higher cell density and simplified manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional 3D stacked semiconductor memory structure is used, then the device can store data using resistive switching elements, but the cell density is limited due to the configuration of electrode structures and current paths
Solution Approach 1:
The word lines are segmented into separate odd and even word lines, and bit lines are divided into local bit lines and source lines. This segmentation allows independent control and optimization of current paths, enabling parallel operation of multiple memory cells and effectively doubling the cell density while managing the complexity through systematic organization
Solution Approach 2:
The patent introduces a vertical stacking dimension by placing odd and even word lines at different heights (Z-direction) above the bit lines. This three-dimensional arrangement creates separate current paths that operate in parallel, increasing the number of accessible memory cells without proportionally increasing planar area, thus improving cell density
2Reliability
If separate odd and even word lines with local source and bit lines are implemented, then the current path resistance is reduced and cell density is doubled, but the device structure becomes more complex
Solution Approach 1:
By segmenting the electrode lines into distinct odd word lines, even word lines, local bit lines, and source lines, each component can be optimized for its specific function. The segmentation creates dedicated current paths that reduce resistance by eliminating shared conductive paths, while the systematic segmentation approach manages structural complexity through clear functional differentiation
Solution Approach 2:
The vertical stacking of odd and even word lines at different Z-heights creates independent three-dimensional current paths. This spatial separation in the vertical dimension reduces current path resistance by providing parallel conduction channels, while the structured vertical arrangement manages the increased structural complexity through regular patterning
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively increases cell density by optimizing the electrode structure and reducing the resistance path, thereby improving data storage efficiency and simplifying the manufacturing process.
Implementation Method 1
by flowing an electric current through the resistive switching element, the resistive switching element is put into a high resistivity state or a low resistivity state
Data Source
AI summary
According to a certain embodiment, the 3D stacked semiconductor memory includes: a first electrode line extending in a first direction orthogonal to the semiconductor substrate; a second electrode line adjacent to the first electrode line in a second direction orthogonal to the first direction, and extending in the first direction; a first variable resistance film extending in the first direction and in contact with the second electrode line; a first semiconductor film in contact with the first variable resistance film and the first electrode line; a first potential applying electrode extending in the second direction and in contact with a first insulator layer; a second semiconductor film in contact with a second variable resistance film and the first electrode line; and a second potential applying electrode extending in the second direction and in contact with a second insulator layer. The first and second potential applying electrodes are electrically different nodes.