3D Memory Channel Contact Structure for Positive Transition Voltage
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Solution Overview
Problem
In 3D memory devices, the high doping of the channel material to reduce resistance leads to negative transition voltage, which is undesirable, and the existing spacer structures between the source and drain inhibit electric field flow, causing memory read failure due to reduced switching efficiency.
Innovation Solution
A contact structure with lower resistance than the channel layer is interposed between the source and drain, and gate extension structures are used to enhance the electric field across the channel layer, allowing for ohmic contact and positive transition voltage while maintaining low resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel material is highly doped to reduce resistance, then contact resistance is reduced, but transition voltage becomes negative which is undesirable
Solution Approach 1:
The channel structure is segmented into undoped regions and doped contact regions. The undoped channel portion maintains positive transition voltage while the doped contact portions provide low resistance connections to source and drain, resolving the contradiction between low contact resistance and positive transition voltage.
Solution Approach 2:
Different doping levels are applied to different regions of the channel. The contact regions are highly doped to reduce contact resistance, while the channel region remains undoped or lightly doped to maintain positive transition voltage, achieving both requirements through localized property variation.
2Manufacturing precision
If spacer structures are placed between source and drain, then device structure is defined, but electric field flow is inhibited causing reduced switching efficiency
Solution Approach 1:
The problematic spacer structures that inhibit electric field flow are completely removed from the device architecture. The source and drain are positioned in direct proximity without intervening spacers, allowing unrestricted electric field flow and high switching efficiency while manufacturing precision is maintained through alternative alignment methods.
Solution Approach 2:
Device structure definition is achieved through vertical layering and epitaxial growth rather than horizontal spacer structures. The channel layer is formed between source and drain regions through controlled material deposition, defining device boundaries in the vertical dimension while allowing electric field flow in the horizontal dimension.
Data Source
AI summary
A method of making a semiconductor device includes: providing a stack including a plurality of insulating layers and sacrificial layers alternatively stacking on top of each other, and extending in a first direction; forming a plurality of gate layers by replacing the plurality of sacrificial layers; forming a memory layer extending along the first direction radially inwards of and coupled to the plurality of gate layers in a second direction perpendicular to the first direction; forming a channel layer along the first direction and coupled to a radially inner surface of the memory layer in the second direction; forming a contact structure having a lower resistance than the channel layer; and forming a source and a drain spaced apart from the source in the first direction, such that the contact structure is interposed between the channel layer and at least a portion of the source and/or the drain.