Array Substrate Layout for Low-Resistance TFT Drain Contact
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of thin film transistors in micro display screens for VR and AR devices leads to high contact resistance between the drain electrode and the active layer, resulting in slow responding speeds due to reduced contact area.
Innovation Solution
The array substrate design includes an active layer with specific connection segments that overlap with data lines, increasing the contact area between the drain electrode and the active layer, thereby reducing contact resistance and improving responding speed. This design involves a first connection segment overlapping with the data line, a second connection segment partially overlapping and extending between adjacent data lines, and a third connection segment located between data lines, with controlled angles to optimize contact area and aperture ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the size of thin film transistors is compressed to increase resolution, then pixel pitch and shading area are reduced, but contact area between drain electrode and active layer becomes smaller leading to high contact resistance
Solution Approach 1:
The patent extends the active layer in the vertical dimension by creating connection segments that protrude from the substrate surface. The first connection segment extends from the substrate toward the drain electrode, and the second connection segment extends further to increase the contact area with the drain electrode, effectively utilizing the third dimension to solve the contact resistance problem without increasing the planar footprint.
Solution Approach 2:
The active layer is divided into multiple functional segments: a first connection segment that connects to the source electrode, a second connection segment that contacts the drain electrode, and a third connection segment that serves as the channel. This segmentation allows each part to be optimized for its specific function, with the connection segments designed to maximize contact area while the channel segment maintains proper dimensions for transistor operation.
2Measurement precision
If the size of thin film transistors is compressed to increase resolution, then pixel pitch is reduced, but responding speed of thin film transistors decreases due to high contact resistance
Solution Approach 1:
The active layer connection segments extend in the vertical dimension to increase contact area with the drain electrode. The first connection segment protrudes from the substrate surface, and the second connection segment extends further upward, creating a larger contact interface that reduces contact resistance and improves charge carrier transport, thereby enhancing transistor responding speed without increasing pixel pitch.
3Area of stationary object
If data lines and scan lines are reduced to minimize shading area, then aperture ratio is improved, but manufacturing complexity increases due to precise positioning requirements
Solution Approach 1:
The active layer is designed with different local structures in different regions: the connection segments have extended dimensions to maximize contact area, while the channel segment maintains precise dimensional control for proper transistor operation. This local differentiation allows the structure to serve multiple functions with a single formation process, reducing manufacturing complexity despite the varied geometries.
Data Source
AI summary
Embodiment of the present application discloses an array substrate and a display panel. An active layer includes a first connection segment, a second connection segment, and a third connection segment connected in sequence. A part of the second connection segment of the active layer overlaps with a data line, and another part of the second connection segment locates between two adjacent data lines. The third connection segment locates between the two adjacent data lines. A drain electrode contacts a part of the active layer exposed between the two adjacent data lines.