FinFET ESD Structure With Fin-Cut Isolation for Compact Protection
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Solution Overview
Problem
Semiconductor devices are vulnerable to static electricity, which can cause damage due to high instantaneous voltages, and existing ESD devices are bulky and inefficient in managing static discharge, especially as chip sizes decrease in highly integrated electronic devices.
Innovation Solution
An electrostatic discharge (ESD) device with a fin structure and fin-cut isolation region is developed, featuring a well in a substrate with conductive impurity regions and a low turn-on voltage, allowing for efficient static discharge while maintaining a small size and low on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD device structures are used, then static electricity protection function is provided, but device size becomes large
Solution Approach 1:
The patent transitions from a planar ESD device structure to a three-dimensional FinFET structure with vertical fins extending from the substrate. This dimensional change allows the ESD protection function to be achieved within a smaller footprint area by utilizing the vertical space, thereby resolving the contradiction between providing adequate protection and minimizing device size.
Solution Approach 2:
The ESD device is segmented into multiple fins that are spaced apart from one another, rather than using a single large continuous structure. This segmentation allows the ESD protection function to be distributed across multiple smaller units, achieving the same protection level with reduced overall device area.
2Area of stationary object
If ESD device size is reduced for high integration, then chip size decreases, but static electricity tolerance may be compromised
Solution Approach 1:
The patent changes key structural parameters by introducing vertical fins with specific heights and spacing, and by configuring doped regions at different depths within the fins. These parameter changes enable the ESD device to maintain high protection efficiency in a compact form factor, allowing chip size reduction without compromising static electricity tolerance.
Solution Approach 2:
By moving from a two-dimensional planar structure to a three-dimensional FinFET structure, the patent achieves higher integration density while maintaining or improving ESD protection performance. The vertical dimension provides additional space for creating effective protection paths without increasing the lateral chip footprint.
3Area of stationary object
If ESD device is made compact, then area is reduced, but on-resistance increases
Solution Approach 1:
The vertical fin structure provides additional conduction paths in the vertical dimension, compensating for the reduced lateral area. The doped regions extending vertically through the fins create low-resistance pathways that maintain low on-resistance despite the compact device footprint.
Solution Approach 2:
The patent applies localized high-concentration doping in specific regions of the fins, particularly near the surface and at strategic depths. This local quality enhancement creates low-resistance contact regions that offset the increased resistance that would normally result from reduced device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The ESD device effectively protects semiconductor devices from static electricity by providing a small size, low turn-on voltage, and low on-resistance, enhancing the power performance area and reliability of electronic devices.
Implementation Method 1
a fin-cut isolation region disposed between the first conductive impurity region and the second conductive impurity region in the first direction in each of the plurality of fins to cut each of the plurality of fins into at least a first fin portion and a second fin portion
Implementation Method 2
a first conductive impurity region formed by doping a portion of each of the plurality of fins with first conductive impurities; a second conductive impurity region formed by doping a portion of each of the plurality of fins with second conductive impurities
Data Source
AI summary
An electrostatic discharge (ESD) device having a small size, a low turn-on voltage, and a low on resistance and an ESD protection circuit including the ESD device are provided. The ESD device includes a well formed in a substrate to have a first conductive type, an active region being defined at an upper portion of the substrate, a plurality of fins extending in a first direction to have a structure protruding from the substrate, a first conductive impurity region formed with first conductive impurities, a second conductive impurity region formed with second conductive impurities, and a fin-cut isolation region disposed between the first conductive impurity region and the second conductive impurity region in the first direction to cut each fin, wherein a bottom surface of the fin-cut isolation region is higher than a bottom surface of the active region.