3D Semiconductor Memory Vertical Channel Integration
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Solution Overview
Problem
Traditional two-dimensional semiconductor memory devices face limitations in increasing integration degree due to high equipment costs for forming fine patterns, which restricts cost-effective manufacturing and performance enhancement.
Innovation Solution
A three-dimensional semiconductor memory device is developed with alternately stacked word lines and gate interlayer insulation layers, featuring a vertical channel layer and channel pad on a semiconductor substrate, along with bit lines and insulation pillars, to enhance integration density and reduce manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional planar memory devices use fine pattern formation techniques to increase integration degree, then integration density improves, but equipment cost increases significantly
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional vertical memory structures. Word lines are formed vertically extending from the substrate, and memory cells are stacked in multiple layers, utilizing the third dimension (height) to increase integration density without requiring finer lateral patterning, thereby avoiding the need for expensive hyper-fine pattern equipment
2Manufacturing precision
If three-dimensional memory structures are formed to increase integration density, then substrate area utilization improves, but device complexity increases
Solution Approach 1:
The three-dimensional memory structure is divided into multiple stacked layers, with each layer containing word lines, gate interlayer insulation layers, and memory cells. This segmentation allows the complex 3D structure to be manufactured through repeated application of standard 2D fabrication processes, reducing overall complexity
Solution Approach 2:
The word lines serve multiple functions: they act as gate electrodes for controlling current flow in vertical channels, provide electrical connections between stacked memory cell layers, and enable selective addressing of different memory regions. This multi-functionality reduces the need for additional dedicated structures
Data Source
AI summary
A three-dimensional semiconductor memory device includes word lines and gate interlayer insulation layers that are alternatively stacked on a semiconductor substrate while extending in a horizontal direction, a vertical channel layer that faces the word lines and extends upwardly from the semiconductor substrate, and a channel pad that extends from the vertical channel layer and is disposed on an uppermost gate interlayer insulation layer of the gate interlayer insulation layers.