Memory Cell Via Layout for MTJ Alignment and Connectivity

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Solution Overview

Problem

The challenge in semiconductor device fabrication lies in reducing process defects and improving electrical characteristics, particularly in the integration of magnetic tunnel junctions within semiconductor memory devices, which require precise alignment and connectivity to ensure efficient data storage and reading operations.

Innovation Solution

The semiconductor device incorporates data storage patterns and conductive lines with strategically placed cell via contacts that connect dummy data storage patterns, allowing for improved electrical connectivity and reduced fabrication defects by using a specific layout and etching processes to form magnetic tunnel junctions between conductive lines and data storage patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If cell via contacts are placed between first cell conductive lines to connect dummy data storage patterns, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvealignment precisionVSAvoidstructure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The via contact structure is segmented into two distinct parts: a first via contact portion extending between the first cell conductive lines, and a second via contact portion extending between dummy data storage patterns. This segmentation allows each portion to be independently optimized for its specific function, improving alignment precision while maintaining manageable structural complexity through modular design.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The via contact structure serves as an intermediary element that connects multiple components (first cell conductive lines and dummy data storage patterns) that would otherwise be difficult to align directly. By introducing this intermediate connecting structure, the patent enables precise alignment and electrical connection between components that are spatially separated, resolving the contradiction between manufacturing precision and device complexity.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If magnetic tunnel junctions are integrated with precise alignment between conductive lines and data storage patterns, then reliability is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveelectrical connectivityVSAvoidalignment precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The via contact is divided into functionally distinct segments (first via contact portion for connecting conductive lines, second via contact portion for connecting dummy data storage patterns). This segmentation allows the manufacturing process to target each segment with appropriate precision requirements, ensuring reliable electrical connectivity while distributing the overall precision burden across multiple manageable steps rather than requiring single-step ultra-precise alignment.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The via contact structure is designed and positioned in advance to establish predetermined connection points between conductive lines and data storage patterns. By performing the alignment and connection preparation beforehand through the structured via contact design, the patent ensures reliable electrical connectivity for the magnetic tunnel junctions while managing precision requirements through pre-planned connection geometry.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP4468352A1Semiconductor device
Publication Date: 2024.11.27 SAMSUNG ELECTRONICS CO LTD
  • EP4468352A1 patent drawingFigure 1
  • EP4468352A1 patent drawingFigure 2
  • EP4468352A1 patent drawingFigure 3

AI summary

A semiconductor device includes data storage patterns (DS) provided on a substrate (100) and spaced apart from each other in first (D1) and second directions (D2) parallel to a top surface of the substrate, first cell conductive lines (192) provided on the data storage patterns (DS), extended in the first direction (D1), and spaced apart from each other in the second direction (D2), each of the first cell conductive lines (192) being connected to corresponding ones of the data storage patterns (DS), which are spaced apart from each other in the first direction (D1), and cell via contacts (200) spaced apart from each other in the first direction (D1), between the first cell conductive lines (192). Each of the cell via contacts (200) between the first cell conductive lines (192) extends in the second direction (D2) and is connected to dummy data storage patterns (DS_d) of the data storage patterns, which are spaced apart from each other in the second direction (D2).