Vertical Semiconductor Devices with Stacked Insulating and Polycrystalline Silicon Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration density of semiconductor devices is limited by the need for expensive fine patterning technologies in two-dimensional planar devices, prompting the development of vertical semiconductor devices to increase integration density, but these require innovative fabrication methods to reduce costs and enhance performance.
Innovation Solution
A method involving the stacking of insulating and polycrystalline silicon layers on a substrate to form vertical channels, with trench formation and doping, followed by a silicidation process to create metal silicide patterns, allowing for the formation of vertically integrated semiconductor devices with varying impurity concentrations and etch depths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If fine patterning technologies are used to increase integration density of two-dimensional planar semiconductor devices, then integration density is improved, but manufacturing cost increases due to expensive apparatuses
Solution Approach 1:
The patent transitions from two-dimensional planar device architecture to three-dimensional vertical device architecture. Multiple semiconductor layers are stacked vertically to form vertical channels that extend through insulating layers, enabling integration density improvement without requiring expensive fine patterning technologies. The vertical structure allows cells to be arranged in the third dimension, effectively increasing the quantity of functional elements per unit area.
2Quantity of substance
If vertical type semiconductor devices are fabricated to increase integration density, then integration density is improved, but fabrication complexity increases requiring innovative fabrication methods
Solution Approach 1:
The fabrication process is segmented into distinct sequential steps: forming alternating insulating and semiconductor layers, creating trenches through the stacked structure, selectively removing portions of layers, and forming vertical channels. Each step operates on a simplified two-dimensional cross-section that eventually builds into three-dimensional vertical structures, making the complex fabrication process more manageable and controllable.
Solution Approach 2:
The patent forms the complete stacked structure of alternating insulating layers and semiconductor layers before creating trenches and performing selective removal. This preliminary formation of the layered architecture establishes a template that guides subsequent fabrication steps, ensuring that vertical channels are formed with proper spacing and alignment without requiring complex real-time adjustments during manufacturing.
3Manufacturing precision
If trenches are expanded to expose the first insulating layer by removing polycrystalline silicon layers, then vertical channel formation is enabled, but material loss increases
Solution Approach 1:
The patent applies selective removal to different polycrystalline silicon layers with different doping concentrations. The first polycrystalline silicon layer (with lower doping concentration) is selectively removed to form trenches and expose the first insulating layer, while the second and third polycrystalline silicon layers (with higher doping concentrations) are preserved to form the vertical channel structure. This local differentiation based on doping concentration enables precise control over which materials are removed and which are retained.
Solution Approach 2:
The patent utilizes doping concentration as a distinguishing parameter to enable selective etching. By varying the doping concentration across different polycrystalline silicon layers, the invention creates etch selectivity that allows one layer to be removed while preserving others. This parameter change transforms a potential material loss problem into a controlled fabrication advantage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of high-density semiconductor devices with improved electrical characteristics and reduced manufacturing costs by leveraging the vertical structure and doping profiles, enhancing integration density and performance.
Implementation Method 1
The expanding of the trench may include performing a wet etch process using an etchant including aqueous ammonia
Implementation Method 2
the transforming may include forming a metal layer on an inner wall of the expanded trench and performing a silicidation process
Implementation Method 3
the second polycrystalline silicon layers and the third polycrystalline silicon layer may be doped with impurities
Data Source
AI summary
Methods of forming semiconductor devices including vertical channels and semiconductor devices formed using such methods are provided. The methods may include forming a stack including a plurality of insulating patterns alternating with a plurality of conductive patterns on an upper surface of a substrate and forming a hole through the stack. The hole may expose sidewalls of the plurality of insulating patterns and the plurality of conductive patterns. The sidewalls of the plurality of insulating patterns may be aligned along a first plane that is slanted with respect to the upper surface of the substrate, and midpoints of the respective sidewalls of the plurality of conductive patterns may be aligned along a second plane that is substantially perpendicular to the upper surface of the substrate.