Hybrid TFT Array Substrate Layout With Fewer Mask Plates
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Solution Overview
Problem
Existing array substrates face challenges in achieving enhanced display quality due to limitations in switching speed, driving current, leakage current, and uniformity of thin film transistors, particularly requiring complex fabrication processes with multiple mask plates.
Innovation Solution
The use of a combination of metal oxide transistors as bottom-gate type transistors in the display area and polysilicon transistors as both bottom-gate type transistors in the peripheral area, with polycrystalline silicon active layers, simplifying the fabrication process by reducing the number of mask plates required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If metal oxide transistors are used in the display area, then switching speed and uniformity are improved, but fabrication complexity increases due to requiring multiple mask plates
Solution Approach 1:
The array substrate is divided into two distinct areas with different transistor types: the display area uses metal oxide transistors for high switching speed and low leakage current, while the peripheral area uses polysilicon transistors for high driving current. This segmentation allows each region to be optimized independently, achieving high performance in the display area without requiring complex fabrication processes for the entire substrate.
Solution Approach 2:
Different transistor structures are applied to different locations based on functional requirements. Metal oxide transistors with specific gate structures are used only where high switching speed is critical (display area), while polysilicon transistors are used in the peripheral area where high driving current is needed. This local differentiation optimizes performance while simplifying overall fabrication.
2Power
If polysilicon transistors are used in the peripheral area, then driving current is improved, but leakage current increases
Solution Approach 1:
The substrate is segmented into display area and peripheral area, each using transistor types optimized for their specific functions. Polysilicon transistors in the peripheral area provide high driving current for signal processing, while metal oxide transistors in the display area provide low leakage current for pixel control, thus isolating the leakage issue to non-critical regions.
Solution Approach 2:
The peripheral area acts as an intermediary zone that handles high-current signal processing tasks, isolating the polysilicon transistors' higher leakage characteristics from the display area where low leakage is critical. This spatial separation allows each transistor type to operate in its optimal performance range.
Data Source
Figure 1A~1C
Figure 2~4
Figure 5A~5E
AI summary
The present application discloses an array substrate, a display apparatus and a method of fabricating an array substrate. The array substrate has a plurality of first bottom-gate type thin film transistors each of which including a metal oxide active layer and a plurality of second bottom-gate type thin film transistors each of which including a silicon active layer.