Charge Trap Memory Self-Heating Circuit Alternating Bias
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Solution Overview
Problem
Charge trap memory devices face limitations in endurance due to insufficient erase operations, high power consumption, metal migration, and time-dependent dielectric breakdown, especially during multi-time programmable memory applications.
Innovation Solution
A semiconductor memory structure incorporating a charge trap transistor with a self-heating circuit that alternates bias direction between the source and drain regions to enhance erase and programming operations, reducing current flow in one direction and sharing high bias voltage between gate-drain and gate-source, thereby improving erase efficiency and reducing breakdown risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional erase operations are applied in charge trap memory devices, then the erase function is achieved, but the endurance is limited due to insufficient erase capability
Solution Approach 1:
The patent applies periodic action by implementing self-heating through alternating current cycles that periodically reverse bias between source and drain regions. This periodic heating and cooling enables progressive charge detrapping from the dielectric, achieving thorough erase operations while maintaining device reliability over multiple program/erase cycles
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting the bias voltage parameters between source and drain regions during erase operations. By varying the voltage magnitude and polarity in controlled steps, the method achieves complete charge removal from the dielectric without causing dielectric breakdown, thereby improving both erase capability and device endurance
2Productivity
If high drain bias is applied during programming operations, then programming efficiency is improved, but the risk of dielectric breakdown increases
Solution Approach 1:
The patent implements periodic action by applying alternating current cycles that periodically reverse the bias between source and drain regions. This periodic reversal prevents sustained high electric field stress on the dielectric while still enabling efficient charge injection during the forward bias phase, thereby maintaining programming efficiency without increasing breakdown risk
Solution Approach 2:
The patent applies preliminary anti-action by using the self-heating effect to pre-heat the channel region before charge injection. This preliminary heating facilitates charge trapping at lower applied voltages, reducing the need for high drain bias and consequently lowering the risk of dielectric breakdown while maintaining programming efficiency
3Duration of action of stationary object
If continuous current flows in one direction through the charge trap transistor, then device operation is maintained, but metal migration occurs reducing device lifetime
Solution Approach 1:
The patent applies periodic action by implementing alternating current cycles that periodically reverse the current direction between source and drain regions. This periodic reversal prevents unidirectional metal ion drift that causes migration, while maintaining continuous device operation. The alternating stress also promotes uniform metal distribution and reduces localized accumulation
Solution Approach 2:
The patent uses inversion by reversing the conventional unidirectional current flow and instead applying alternating current that periodically inverts the bias polarity. This inversion of the current direction prevents cumulative metal migration effects that occur with continuous unidirectional flow, thereby extending device lifetime while maintaining operational continuity
4Productivity
If high power is consumed during erase operations, then erase effectiveness is improved, but overall power consumption increases
Solution Approach 1:
The patent applies self-service by utilizing the device's own current flow to generate heat through Joule heating in the channel region. This self-generated heat eliminates the need for external heating mechanisms, achieving thorough erase operations without additional power consumption. The method converts the necessary operational current into useful thermal energy for charge detrapping
Solution Approach 2:
The patent utilizes phase transitions by leveraging the thermal effects that occur during current flow to induce phase changes in charge distribution within the dielectric. The self-heating causes thermal expansion and increased charge mobility, facilitating detrapping without requiring external power input, thereby maintaining erase effectiveness while minimizing additional power consumption
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly increases the program/erase endurance to over 1000 cycles, mitigates tungsten migration, and reduces the risk of dielectric breakdown, while improving uniformity and reliability of erase operations.
Implementation Method 1
a self-heating circuit which selectively applies an alternating bias direction between the source region and the drain region of the charge trap transistor
Data Source
AI summary
The present disclosure generally relates to semiconductor structures and, more particularly, to charge trap memory devices and methods of manufacture and operation. The semiconductor memory includes: a charge trap transistor comprising a gate structure, a source region and a drain region; and a self-heating circuit which selectively applies an alternating bias direction between the source region and the drain region of the charge trap transistor to provide an erase operation or a programming operation of the charge trap transistor.