3D Integrated Circuit Oxide-to-Oxide Bonding Reliability
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Solution Overview
Problem
Conventional three-dimensional integrated circuit fabrication techniques face challenges due to surface unevenness and damage from substrate removal processes, which can affect the quality of oxide-to-oxide bonding between device layers, leading to unreliable bonds.
Innovation Solution
The technique involves forming a three-dimensional integrated circuit with a bottom device layer and a top device layer, where the top layer has a thick buried oxide layer to protect the analog CMOS and photonics circuitry during substrate removal, and an oxide-to-oxide bond is formed between the bonding oxide layers of both layers, allowing for face-to-face bonding and minimizing damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If substrate removal is performed by grinding or selective etching to enable oxide-to-oxide bonding, then the insulator (oxide) can be exposed for bonding, but the exposed insulator surface becomes damaged and uneven, negatively affecting bond quality
Solution Approach 1:
A handle wafer is introduced as an intermediary carrier that supports the device layer during substrate removal and bonding processes. The handle wafer provides a stable surface for handling and enables the device layer to be bonded to another device layer without direct exposure to damaging removal processes, thus protecting the insulator surface quality while enabling oxide-to-oxide bonding
Solution Approach 2:
The handle wafer is attached to the device layer in advance before substrate removal. This preliminary attachment provides mechanical support and protection during subsequent substrate removal operations, preventing direct damage to the insulator surface and maintaining surface uniformity for high-quality bonding
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the reliability and quality of the oxide-to-oxide bond, reduces surface irregularities, and protects the circuitry during substrate removal, resulting in improved three-dimensional integrated circuit integration.
Implementation Method 1
The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer
Data Source
AI summary
Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a substrate; a digital CMOS circuitry layer adjacent to the substrate; and a first bonding oxide layer adjacent to a side of the digital CMOS circuitry layer opposite the substrate. The top device layer comprises an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer having a buried oxide (BOX) with a thickness of greater than or equal to about 0.5 micrometers; and a second bonding oxide layer adjacent to the analog CMOS and photonics circuitry layer. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.