3D Integrated Circuit Fabrication via Sacrificial Layer Alignment
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Solution Overview
Problem
Current methods for producing three-dimensional integrated circuits face challenges such as alignment limitations, thermal budget constraints, and congestion in electrical interconnection levels, which restrict integration density and efficiency.
Innovation Solution
A method involving the production of MOS devices on substrates with multiple semiconductor layers, where active zones of MOS devices are formed in specific layers with a third material layer, allowing for independent production and alignment of device levels, and enabling efficient electrical interconnections without thermal budget limitations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If parallel integration of different levels is used to increase integration density, then integration density is improved, but alignment precision deteriorates because current alignment performance is limited to a few microns
Solution Approach 1:
The patent applies preliminary action by forming the third material layer between the first and second semiconductor layers before fabricating the MOS devices. This pre-positioned layer serves as a reference structure that enables precise alignment during subsequent bonding operations, allowing integration density to improve while maintaining alignment precision through pre-established alignment features
Solution Approach 2:
The third material layer acts as an intermediary element between the first and second semiconductor layers. This intermediate layer facilitates precise alignment and bonding by providing a stable reference plane and enabling controlled positioning, thus resolving the alignment precision issue while maintaining high integration density
2Manufacturing precision
If sequential integration of different levels is used to improve alignment precision, then alignment precision is improved, but productivity deteriorates because levels must be fabricated one after the other
Solution Approach 1:
The patent segments the integration process into independent parallel fabrication stages. Different semiconductor layers are prepared separately with their respective MOS devices, then combined through bonding. This segmentation allows each layer to be optimized independently while maintaining high alignment precision through the third material layer reference structure, thereby improving overall productivity
Solution Approach 2:
The patent transitions from sequential one-dimensional processing to parallel multi-dimensional processing by fabricating multiple semiconductor layers simultaneously in different spatial planes. The third material layer provides a reference structure that enables precise three-dimensional positioning, allowing parallel fabrication while maintaining alignment precision
3Reliability
If thermal budgets are reduced to protect lower levels during sequential integration, then reliability is improved, but device performance deteriorates
Solution Approach 1:
The third material layer is formed preliminarily between the semiconductor layers before device fabrication and bonding. This pre-positioned layer acts as a thermal and structural buffer that protects lower-level devices during subsequent high-temperature processing of upper layers, enabling both high reliability and optimal device performance without thermal budget constraints
4Quantity of substance
If parallel integration with bonding is used to increase integration density, then integration density is improved, but device complexity increases due to alignment and bonding process requirements
Solution Approach 1:
The third material layer serves as an intermediary reference structure that simplifies the bonding process. By providing pre-formed alignment features and a stable bonding interface, it reduces the complexity of alignment and bonding operations while enabling high integration density through parallel integration of multiple layers
Data Source
Figure 1~2B
Figure 3~4
Figure 5A~5B
AI summary
The method involves producing a substrate comprising semiconductor layers between which a third material layer i.e. sacrificial layer, is placed. Metal oxide semiconductor (MOS) transistor (140) e.g. P channel MOS transistor, whose active area is formed in a portion of one of the semiconductor layers, is formed. Another MOS transistor (172), whose active area is formed in a silicon portion (152) of another semiconductor layer, is formed. The active area of the latter MOS device is placed between a gate material (162) of the latter MOS transistor and the active area of the former transistor.