Solid-State Devices TRIZ Cases

A stiffening structure embedded with the lead frame improves chip fixation and electrical contacting while keeping optoelectronic package design flexible.

Collimated light from multiple pixels is redirected to intersect at different focal planes, reducing near-eye display optics weight and cost.

By embedding the control semiconductor in the base, this pixel package avoids LED light blockage and keeps emission patterns uniform.

Spacer-defined dummy patterns create hard-mask via openings for SRAM contact bars, improving FinFET density and pattern precision.

Laminated semiconductor layers and shared wiring improve near-infrared sensitivity while avoiding thicker sensor layers and costly process steps.

Overflow-underflow delay control aligns core and interface dies in stacked memory, cutting unnecessary timing delay updates during read and write.

Vertical trench grids isolate SPAD pixels and add optical shielding to curb edge-triggered avalanches and cross-talk in single-photon imaging.

Strategic quadrant chip placement improves substrate use, heat dissipation, and pin efficiency while simplifying IC photomask manufacturing.

Bidirectional touch signal line routing with protected spacing and curved sections cuts ESD risk, parasitic capacitance, and pixel area loss.

Selective pixel resets during one frame extend imager dynamic range, limiting saturation, noise, and extra memory use.

Cryogenic wafer cooling boosts ion channeling during implantation, enabling deeper CMOS photodiode wells for better infrared sensitivity.

Overlapped repair lines on separate insulated layers fix defective subpixels while preserving transparent display emission and transmission area.

Spaced support arms reduce molten silicon adhesion during SiC wafer fabrication, improving drainage and substrate separation.

A squarylium core-shell resin improves chemical resistance while enabling fine color filter patterning after curing and thermal processing.

Parallel partial and added signal readout enables HDR expansion and accurate phase difference AF in the same frame, even in long exposures.

Controlled melt viscosity and silane-modified adhesion limit resin flow during hot pressing, keeping display encapsulant thickness uniform.

A light absorbing and reflecting assembly boosts top-emission display output while suppressing ambient light reflection without polarizer loss.

Selective openings in the buffer dielectric let a pixel metal grid contact the substrate and trench fill structure to improve electrical performance.

An etch-resistant barrier region between contact regions blocks hot phosphoric acid over-etch from exposing or shorting memory control circuitry.

A light guider and top light blocker spread LED output across the pixel area to reduce point-source visibility and luminance unevenness.

Cross-coupled transistors discharge static charge between adjacent array signal lines, cutting short-circuit risk without extra wiring.

Standardized power and differential-signal connectors let one imaging control substrate support multiple imaging elements with simpler routing and lower cost.

Self-aligned capacitor pillars and conductive lines improve horizontal spacing precision, cut cross-talk, and preserve non-volatile reads.

A patterned adhesion layer formed by lithography strengthens LED unit bonding, preserves alignment, and improves electrical connection quality.

A diffusion layer between resin and patterned phosphor preserves luminance and pattern contrast in vehicle lighting without added thickness.

Separate FinFET and high-voltage regions with metal-gate resistor formation help curb leakage and improve breakdown voltage control.

A 70-85° insulating-layer via and black partition structures suppress reflective color bands and improve color uniformity without a polarizer.

Magnetic attraction combined with capillary action aligns micro LEDs to pixel regions, cutting misalignment defects and improving display lifespan.

A through-hole bonding structure integrates touch and display driving in one chip assembly, cutting panel thickness and bezel width.

A parallel OLED blue unit with common blue layers and charge connecting layers improves lifetime and efficiency while avoiding tandem process complexity.

MicroLEDs, waveguides, and substrate photodetectors are integrated on IC chips to raise interconnect density while cutting latency and power.

Multiple articulating transfer heads enable parallel micro device pick-and-place, cutting cycle time and travel distance across substrates.

An intermediate cap layer smooths the Ge-Si band offset, cutting dark current and improving CMOS time-of-flight signal accuracy.

Small-area OTS arrays with series resistors spread ESD current to cut die area, avoid thermal runaway, and protect multi-supply ICs.

A multilayer color compensation stack lets a silver reflective electrode boost display brightness while limiting yellow color shift toward white reflection.

Shape memory alloy pixel electrodes protrude during drying to redirect climbing ink and keep OLED organic layers uniform.

Low-resistance edge metal films stabilize transparent electrode potential in OLED panels, reducing voltage drop, shedding, and image nonuniformity.

A light shielding portion between the OLED emitter and TFT blocks irradiated light, preventing active-layer deterioration and extending display life.

Partition walls and efficiency-matched sub-pixel areas improve micro LED color purity, viewing-angle stability, and replacement handling.

Adaptive compensation maps and layer footprint tuning reduce OLED sub-pixel optical cross-talk and visible color shift across viewing conditions.

Overlapping signal lines across multiple metal layers shrink gate driver routing width and enable narrower LCD panel frames.

Selective barrier coverage on a stepped bit line contact lowers resistance at the active region while simplifying DRAM patterning.

A stacked active-layer TFT layout extends channel length in VR array substrates, improving stability without increasing substrate area.

A single tapered contact hole links polysilicon and oxide TFT source/drain regions to cut circuit area, simplify interconnects, and support high-resolution displays.

A shared deposition step forms reflective bank electrodes and transistor electrodes together, cutting masks, cost, and boosting light output.