Mesa-Shaped Insulating Layer for Monolithic MOSFET Integration
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Solution Overview
Problem
The use of MOSFETs with thick buried oxide films in semiconductor devices leads to height differences between the SOI substrate and the support substrate, causing lithography focus deviations and complicating etching processes, resulting in reduced accuracy and yield.
Innovation Solution
A semiconductor device design where the first MOSFET is formed on a high-resistance substrate with a second MOSFET monolithically integrated, featuring a mesa-shaped insulating layer formed by trenching and oxidation, ensuring the insulating layer does not protrude beyond the semiconductor layers, thereby reducing height differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MOSFETs with thick buried oxide films are used to reduce parasitic capacitance and improve high-frequency characteristics, then transmission loss and harmonic distortion are reduced, but height differences between SOI substrate and support substrate increase causing lithography focus deviations and etching process complications
Solution Approach 1:
The patent introduces a planarization layer (spin-on-glass or CMP-processed insulating layer) to flatten the surface topography created by thick buried oxide films. This adds a dimensional solution (surface flattening) to the height difference problem, enabling subsequent lithography and etching processes to proceed with appropriate focus accuracy while maintaining the beneficial thick oxide structure for high-frequency performance
Solution Approach 2:
The patent uses a planarization layer as an intermediary between the thick buried oxide film structure and the subsequent processing steps. This intermediate layer mediates the conflict by providing a flat working surface for lithography and etching while allowing the underlying thick oxide structure to remain intact for electrical performance
2Reliability
If MOSFET element size is reduced to decrease channel length and lower CR product, then parasitic capacitance and on-resistance are reduced improving high-frequency performance, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent employs thin-film SOI substrate technology with precisely controlled oxide layer thicknesses (buried oxide film thickness of 0.5-2.0 μm and gate oxide film thickness of 5-20 nm) to enable element miniaturization. By changing and optimizing these physical parameters, the patent achieves reduced parasitic capacitance and CR product while maintaining manufacturability through standardized thin-film processing techniques
3Reliability
If thick buried oxide films are formed to suppress support substrate effects, then parasitic capacitance is reduced, but etching conditions become more complicated and yield decreases
Solution Approach 1:
The patent performs preliminary planarization processing (spin-on-glass application or CMP) before etching operations to create a flat surface. This preliminary action prevents etching complications that would otherwise arise from height differences, thereby maintaining both the electrical benefits of thick buried oxide films and high manufacturing yield
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for accurate monolithic integration of transistors on insulating layers, improving dimensional accuracy and yield by minimizing height differences and simplifying the etching process.
Implementation Method 1
forming trenches by etching the first semiconductor layer in the opening formed in the second insulating layer and the third semiconductor layer in the second region, and thereby forming a mesa-shape sandwiched between two trenches in the first semiconductor layer located below the second insulating layer and the third semiconductor layer; forming a first insulating layer by performing oxidation treatment from a side and a bottom of the trenches
Data Source
AI summary
In a semiconductor device, a logic MOSFET and a switch MOSFET are formed in a high-resistance substrate. The logic MOSFET includes an epitaxial layer formed on the high-resistance substrate and a well layer formed on the epitaxial layer. The switch MOSFET includes a LOCOS oxide film formed on the high-resistance substrate, the LOCOS oxide film being sandwiched between trenches and thus having a mesa-shape in its upper part. The switch MOSFET further includes a buried oxide film and a SOI layer formed on the mesa-shape of the LOCOS oxide film. The upper surface of the mesa-shape of the LOCOS oxide film is positioned at the same height as the upper surface of the epitaxial layer.