Vertical Memory Cell Capacitor Layout for Precise Line Spacing
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Solution Overview
Problem
Current memory technologies face challenges in forming arrays of capacitors and memory cells with efficient conductive lines, particularly in maintaining non-volatile states without reversing polarization during read operations, and in achieving precise horizontal spacing and alignment of conductive elements.
Innovation Solution
The method involves forming a vertical stack of transistor material above an insulator, using masks to etch pillars and trenches, and creating capacitors with self-aligned electrodes and conductive lines that interconnect adjacent capacitors, allowing for precise control over horizontal spacing and reducing cross-talk between transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional memory cell arrays are formed with traditional conductive line structures, then manufacturing processes are simpler, but horizontal spacing precision and alignment between conductive elements deteriorate
Solution Approach 1:
The patent transitions from planar conductive lines to three-dimensional conductive pillars that extend vertically through multiple memory cell layers. This dimensional change enables precise horizontal spacing through vertical stacking while maintaining manufacturing feasibility through standard deposition and etching processes adapted for 3D structures.
Solution Approach 2:
Conductive pillars are nested within and between memory cell structures, with pillars extending through insulating layers and positioning themselves in precise horizontal relationships with multiple memory cell rows. This nesting approach achieves complex spacing requirements through hierarchical structural integration.
2Reliability
If ferroelectric capacitor structures are used for non-volatile memory, then data retention is improved, but polarization reversal during read operations causes data integrity issues
Solution Approach 1:
The ferroelectric capacitor is segmented into distinct electrode regions with different functionalities. Read-disturb-free regions are separated from write regions through spatial segmentation, allowing read operations to access one region while write operations occur in another, preventing polarization reversal during reads and preserving data integrity.
Solution Approach 2:
Different regions of the ferroelectric capacitor structure are assigned different electrical properties and functionalities. Certain localized regions are designed with specific electrode configurations and material compositions that prevent polarization reversal during read operations, while other regions maintain full write capability for data storage.
3Quantity of substance
If conductive lines are placed closer together to increase memory density, then storage capacity is improved, but cross-talk between adjacent transistors increases
Solution Approach 1:
Insulating layers and dielectric materials are introduced as intermediary structures between adjacent conductive pillars and transistor gates. These intermediary layers electrically isolate closely-spaced conductive elements, preventing cross-talk while allowing high-density packing of memory cells through reduced horizontal spacing.
Data Source
AI summary
A method used in forming an array of memory cells comprises forming a vertical stack comprising transistor material directly above insulator material. A mask is used to subtractively etch both the transistor material and thereafter the insulator material to form a plurality of pillars that individually comprise the transistor material and the insulator material. The insulator material is laterally-recessed from opposing lateral sides of individual of the pillars selectively relative to the transistor material of the individual pillars. The individual pillars are formed to comprise a first capacitor electrode that is in void space formed from the laterally recessing. Capacitors are formed that individually comprise the first capacitor electrode of the individual pillars. A capacitor insulator is aside the first capacitor electrode of the individual pillars and a second capacitor electrode is laterally-outward of the capacitor insulator. Vertical transistors are formed above the capacitors and individually comprise the transistor material of the individual pillars. Other aspects, including structure independent of method, are disclosed.