Stepped Bit Line Contact Layout for Easier DRAM Patterning
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high integration and performance due to limitations in the design of bit line contacts and contact barrier layers, which affect electrical characteristics and manufacturing productivity.
Innovation Solution
The semiconductor device incorporates a bit line contact with a lower portion and an upper portion of varying widths, where the contact barrier layer covers the bottom and side surfaces of the lower portion but not the upper portion, optimizing the structure to improve electrical characteristics and manufacturing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit line contact structure is used, then the processing is simpler, but the resistance is higher and integration is reduced
Solution Approach 1:
The bit line contact is divided into two distinct portions: a lower portion with a first width and an upper portion with a second width. This segmentation allows each portion to serve different functions - the lower portion provides lower resistance through larger cross-sectional area, while the upper portion facilitates easier patterning and integration with the bit line structure.
Solution Approach 2:
Different portions of the bit line contact have different widths tailored to local requirements. The lower portion has a larger width to minimize resistance at the contact point with the active region, while the upper portion has a smaller width to match the bit line structure dimensions, optimizing both electrical performance and manufacturability.
2Reliability
If the contact barrier layer covers the entire bit line contact, then protection is improved, but patterning difficulty increases
Solution Approach 1:
The contact barrier layer is selectively removed from the upper portion of the bit line contact, retaining it only on the lower portion. This extraction maintains the protective function where it is most needed (at the interface with the active region) while eliminating the patterning difficulties associated with covering the entire contact structure.
Solution Approach 2:
The contact barrier layer is formed to cover the entire bit line contact initially, then selectively removed in a subsequent step. This preliminary formation ensures complete protection during manufacturing, followed by selective removal to achieve the final optimized structure with reduced patterning complexity.
Data Source
AI summary
A semiconductor device includes a substrate including an active region, a word line structure crossing the active region and extending in a first direction, a bit line structure extending in a second direction, a bit line contact electrically connecting a first impurity region of the active region to the bit line structure, a storage node contact on a sidewall of the bit line structure and electrically connected to a second impurity region of the active region, and a contact barrier layer covering at least a portion of the bit line contact, wherein the bit line contact includes a lower portion having a first width and an upper portion on the lower portion and having a second width, the first width is greater than the second width, and the contact barrier layer covers a bottom surface and a side surface of the lower portion.