Thin Film Transistor Substrate Dummy Patterns Annealing Bubbles
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Solution Overview
Problem
The annealing process in thin film transistor manufacturing generates air bubbles in the planarization layer due to out-gassing, leading to reduced surface flatness and potential device reliability issues.
Innovation Solution
Incorporating dummy pattern parts on the same layer as the gate lines in the non-display area, which reduces the area where the planarization layer is formed, thereby minimizing bubble generation during the annealing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the planarization layer is formed over the entire non-display area to improve surface flatness, then the surface flatness is improved, but air bubbles are generated during the annealing process due to out-gassing
Solution Approach 1:
The patent removes the planarization layer from specific regions (dummy pattern areas) where it would generate harmful bubbles during annealing, while maintaining it in areas where surface flatness is critical. This selective extraction eliminates the source of out-gassing bubbles without compromising the overall surface flatness requirement.
Solution Approach 2:
The planarization layer is applied non-uniformly across the substrate - present in display and data pad areas for surface flatness, but absent in dummy pattern areas to prevent bubble generation. This local differentiation of layer presence optimizes both surface flatness and bubble prevention in different regions.
2Object-generated harmful factors
If the planarization layer area is reduced to minimize bubble generation, then air bubble formation is reduced, but surface flatness may be compromised
Solution Approach 1:
The planarization layer is selectively applied only in regions where surface flatness is critical (display area and data pad area), while being omitted from dummy pattern areas where it would cause bubbles. This localized approach maintains surface flatness where needed while eliminating bubble generation sources.
Solution Approach 2:
The planarization layer is extracted from dummy pattern regions to eliminate the source of out-gassing bubbles during annealing, while being retained in functional areas to maintain surface flatness. This selective removal resolves the contradiction between bubble prevention and flatness maintenance.
3Object-generated harmful factors
If dummy pattern parts are added to reduce planarization layer area and minimize bubbles, then bubble generation is reduced, but device complexity increases
Solution Approach 1:
The dummy patterns serve multiple functions: they act as structural fillers to define non-display area boundaries, serve as references for alignment processes, and most importantly, function as regions where the planarization layer is intentionally omitted to prevent bubble generation. This multi-functionality justifies the added structural elements.
Solution Approach 2:
The dummy patterns are formed in advance during the manufacturing process to pre-establish regions where the planarization layer will be omitted. This preliminary structuring allows for controlled bubble prevention without requiring complex real-time adjustments during subsequent processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of dummy pattern parts decreases the areas where the planarization layer is formed, effectively reducing air bubbles and enhancing the surface flatness and reliability of the thin film transistor substrate.
Implementation Method 1
During the manufacture of a display device, an annealing process is typically performed after the thin film transistors have been formed in the display area. The annealing process can remove defects in a semiconductor layer of the thin film transistors, and improve the electrical characteristics of the semiconductor layer.
Implementation Method 2
The annealing process generates air bubbles in the planarization layer due to out-gassing
Data Source
AI summary
A thin film transistor substrate is provided. The thin film transistor substrate includes a display area including a plurality of pixels, wherein the pixels are connected to gate lines and data lines, a gate driver connected to the gate lines, a plurality of data pads connected to the data lines, a plurality of dummy pattern parts formed of a same layer as the gate lines, and a non-display area in which the gate driver, data pads, and dummy pattern parts are disposed, and the dummy pattern parts are disposed in an area within the non-display area where the gate driver is not disposed, and one of the dummy pattern parts is disposed overlapping with the data pads.