Thin-Film Transistor Manufacturing via Merged Oxide Semiconductor and Etch Stop Layer Deposition
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The complex manufacturing process of oxide thin-film transistors, particularly the etch stop layer, increases manufacturing costs and complexity due to the need for multiple masking operations.
Innovation Solution
A method that simplifies the process by forming both the oxide semiconductor and etch stop layers through a single film formation operation, followed by simultaneous patternization and two etching operations to expose the oxide semiconductor layer, reducing the number of pattern formation steps and using a metal oxide etch stop layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the etch stop layer is formed using conventional separate masking operations, then the film characteristics are maintained, but the manufacturing complexity and cost increase due to multiple masking steps
Solution Approach 1:
The patent merges the formation of the oxide semiconductor layer and etch stop layer into a single film deposition step, where both layers are formed simultaneously in one operation rather than through separate masking and deposition steps. This combining of operations directly reduces the total number of masking operations from six to fewer steps, simplifying the manufacturing process while maintaining the necessary film characteristics and structural integrity of the etch stop layer
2Productivity
If separate masking operations are used for oxide semiconductor layer and etch stop layer, then precise pattern control is achieved, but manufacturing time and cost increase
Solution Approach 1:
The patent combines the deposition of oxide semiconductor layer and etch stop layer into one simultaneous film formation operation, eliminating the need for separate masking and deposition cycles for each layer. This merging of operations directly reduces manufacturing cycle time and improves productivity, as the layers are formed in a single continuous process step rather than through multiple sequential operations
Solution Approach 2:
The etch stop layer is formed preliminarily together with the oxide semiconductor layer in the same deposition step, before subsequent patterning operations. This preliminary combined formation ensures that both layers are ready for simultaneous patterning in later steps, reducing the overall manufacturing timeline while maintaining precise pattern control through subsequent etching operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the manufacturing cost and complexity by eliminating one pattern formation operation and improving the film characteristics of oxide thin-film transistors, enhancing processing efficiency.
Implementation Method 1
the etch stop layer is formed through a physical vapor deposition based film formation process
Implementation Method 2
applying a wet etching operation to the patternized oxide semiconductor layer and the etch stop layer
Data Source
AI summary
A method for manufacturing a thin-film transistor includes: forming a first metal layer of a pattern including a gate on a substrate through pattern formation operations; forming a gate insulation layer on the substrate and the first metal layer and forming an oxide semiconductor layer, of which an orthogonal projection is cast on the gate, on the gate insulation layer within a thin-film transistor area and an etch stop layer on the oxide semiconductor layer, in which two etching operations are applied to the patternized oxide semiconductor layer and etch stop layer; forming a patternized second metal layer on the thin-film transistor area and an exposed portion of the gate insulation layer, forming a patternized insulation protection layer on the substrate and the patternized second metal layer, and forming a patternized pixel electrode on the insulation protection layer.