ReRAM Protective Resistance Layer Stabilizing State Transitions
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Solution Overview
Problem
Miniaturization of NAND flash memory devices has led to reliability issues due to unstable transitions between reset and set states in resistance random access memory (ReRAM), causing unstable information storage and reading, primarily attributed to the characteristics of the protective resistance layer which exhibit either ohmic or exponential current-voltage relationships, resulting in excessive electrical stress and inaccurate data retrieval.
Innovation Solution
Incorporating a protective resistance layer with an Esaki diode structure, comprising p+-type and n+-type semiconductor layers with high impurity concentrations, which allows for a voltage-current curve with distinct regions for reading and setting, ensuring low resistance during reading and high resistance during setting, thereby stabilizing the memory cell operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If a protective resistance layer with ohmic or exponential current-voltage characteristics is used in ReRAM, then the memory cell can be miniaturized, but the transitions between reset and set states become unstable causing unreliable information storage and reading
Solution Approach 1:
The patent changes the electrical characteristics of the protective resistance layer by using an Esaki diode structure with specific p+-type and n+-type semiconductor layers. This creates a voltage-current curve with distinct regions (first region with positive differential resistance for reading, second region with negative differential resistance for setting) that stabilizes the memory cell operations and enables reliable state transitions while maintaining miniaturization
Solution Approach 2:
The protective resistance layer is constructed as a composite structure combining p+-type semiconductor layer and n+-type semiconductor layer to form an Esaki diode. This composite material approach creates the unique voltage-current characteristics with both positive and negative differential resistance regions, resolving the stability issue while enabling further miniaturization
2Device complexity
If the protective resistance layer exhibits ohmic or exponential current-voltage characteristics, then the device structure can be simplified, but excessive electrical stress is applied during transitions leading to inaccurate data retrieval
Solution Approach 1:
The patent introduces dynamic control of resistance characteristics through the Esaki diode's voltage-dependent behavior. The protective resistance layer transitions between high resistance state (in second region with negative differential resistance during setting) and low resistance state (in first region with positive differential resistance during reading), dynamically adapting to operational requirements and reducing electrical stress
3Quantity of substance
If miniaturization is pursued in NAND flash memory, then higher capacity can be achieved, but reliability issues arise due to unstable memory cell operations
Solution Approach 1:
By changing the electrical parameters of the protective resistance layer through Esaki diode implementation, the patent stabilizes the voltage-current characteristics during read and set operations. This enables reliable operation of miniaturized memory cells while maintaining high memory capacity through continued miniaturization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively reduces electrical stress during transitions and ensures stable information storage and retrieval by maintaining appropriate resistance states, enhancing the reliability and accuracy of data writing and reading in ReRAM devices.
Implementation Method 1
a voltage-current curve with distinct regions for reading and setting, ensuring low resistance during reading and high resistance during setting
Data Source
AI summary
According to one embodiment, a nonvolatile memory device includes a first wiring, a second wiring, and a memory cell provided between the first wiring and the second wiring. The memory cell includes a memory layer, a rectifying element layer, and a protective resistance layer including a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type.


