Display Terminal Step Minimization via Planarization Layer

The patent introduces a planarization layer that extends laterally beyond the terminal edge in the horizontal dimension, filling the vertical step gap with horizontal material extension. This transforms the vertical step problem into a horizontal filling solution, where the planarization layer covers both the terminal upper face and the interlayer insulating film upper face, creating a flush surface for external circuit substrate mounting.

The planarization layer acts as an intermediary element between the terminal and the interlayer insulating film. It mediates the height difference by providing a transitional surface that connects the two structures, allowing the external circuit substrate to be mounted on a planar surface without direct contact with the stepped interface.

The planarization layer serves multiple functions simultaneously: it provides electrical insulation between the terminal and interlayer insulating film, fills the step gap to create a planar surface, and serves as an adhesive layer for mounting the external circuit substrate. This multi-functionality resolves the contradiction by adding a single element that addresses both manufacturing simplicity and connection reliability.

The patent changes the physical parameters of the planarization layer, including its thickness (greater than the step height), material composition (insulating material), and lateral extent (beyond terminal edge), to transform it from a simple filler into a functional component that ensures reliable connection while maintaining manufacturing feasibility.