SRAM Contact Bar Patterning with Spacer-Derived Hard Masks
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing SRAM devices with fin field effect transistors (Fin FETs) due to complexities in three-dimensional design and fabrication, particularly in achieving high device density, performance, low power consumption, and cost-effectiveness.
Innovation Solution
The method involves forming fin structures and gate electrodes using sequential processes, including the formation of dummy patterns, sidewall spacer layers, and hard mask layers to create precise gate and contact bar structures, enabling the fabrication of SRAM devices with improved fin FETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional Fin FET designs are implemented to increase device density, then device density is improved, but fabrication complexity increases
Solution Approach 1:
The fabrication process is divided into multiple sequential steps including forming first dummy patterns, depositing sidewall spacer layers, removing first dummy patterns, dividing second dummy patterns into plural pieces, and forming gate electrodes. This segmentation of the complex fabrication process into manageable stages enables precise control over Fin FET structures while maintaining high device density.
Solution Approach 2:
Dummy patterns are formed in advance as placeholders to define the positions and dimensions of future Fin FET structures. These preliminary patterns guide subsequent processing steps, including sidewall spacer formation and gate electrode deposition, ensuring precise structural control before actual device formation begins.
2Manufacturing precision
If sequential processes with multiple dummy patterns are used to create precise gate structures, then manufacturing precision is improved, but productivity decreases
Solution Approach 1:
Multiple dummy patterns (first dummy patterns and second dummy patterns divided into plural pieces) are utilized in sequence to simultaneously define both the gate electrode positions and the Fin FET structural dimensions. This merging of patterning functions into a unified sequential process achieves high manufacturing precision without requiring separate alignment steps for each feature.
Solution Approach 2:
Sidewall spacer layers serve as intermediary structures that transfer the dimensional information from the removed first dummy patterns to the final Fin FET structures. These spacer layers act as self-aligned masks and structural templates, ensuring precise gate and contact bar formation while simplifying subsequent processing steps.
3Reliability
If complex dummy pattern formation and removal processes are implemented, then device performance is improved, but loss of time increases
Solution Approach 1:
First dummy patterns are intentionally formed, utilized to define structural dimensions, and then completely removed after serving their purpose. Second dummy patterns are divided into plural pieces and removed selectively to form precise gate structures. This discarding of temporary placeholder structures enables precise device formation while allowing process optimization through material recovery and waste reduction.
Data Source
AI summary
In a method of manufacturing an SRAM device, an insulating layer is formed over a substrate. First dummy patterns are formed over the insulating layer. Sidewall spacer layers, as second dummy patterns, are formed on sidewalls of the first dummy patterns. The first dummy patterns are removed, thereby leaving the second dummy patterns over the insulating layer. After removing the first dummy patterns, the second dummy patterns are divided. A mask layer is formed over the insulating layer and between the divided second dummy patterns. After forming the mask layer, the divided second dummy patterns are removed, thereby forming a hard mask layer having openings that correspond to the patterned second dummy patterns. The insulating layer is formed by using the hard mask layer as an etching mask, thereby forming via openings in the insulating layer. A conductive material is filled in the via openings, thereby forming contact bars.