Stacked Memory Timing Alignment with Overflow-Underflow Delay Control
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Solution Overview
Problem
In stacked semiconductor memory devices, achieving precise timing alignment of data between core dies and an interface die is challenging due to varying propagation times caused by different distances and temperatures, leading to suboptimal delays that can result in longer-than-needed alignment.
Innovation Solution
The implementation of a variable delay circuit in the interface die and core dies, along with a state machine that uses an underflow/overflow process to set alignment delays, allowing for sustained drift adjustments and rapid alignment without averaging, ensures that delays are only adjusted when necessary, optimizing the alignment process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If fixed delay circuits are used for timing alignment, then the alignment process is simple, but the alignment precision is insufficient due to varying propagation times
Solution Approach 1:
The patent applies dynamics by transitioning from fixed delay circuits to variable delay circuits that can dynamically adjust their delay values. The interface die and core dies incorporate delay circuits whose delay amounts can be modified based on measured propagation times, allowing the system to adapt to varying conditions and achieve precise timing alignment while managing complexity through controlled adaptability.
2Reliability
If delay adjustments are made frequently to maintain alignment, then the timing alignment remains precise, but the overhead and complexity of the alignment process increases
Solution Approach 1:
The patent implements feedback mechanisms where the system measures actual data propagation times between core dies and the interface die, then uses these measurements to adjust delay circuit values. This closed-loop feedback approach ensures timing alignment remains precise and reliable while avoiding unnecessary adjustments, thereby reducing the time and overhead associated with the alignment process.
Solution Approach 2:
The patent applies preliminary action by performing delay measurements and adjustments during initialization or idle periods before actual data transfer operations begin. The system pre-determines optimal delay values based on measured propagation times, so that when data transfer occurs, the alignment is already optimized without requiring time-consuming adjustments during active operations.
Data Source
AI summary
Apparatuses, systems, and methods for data timing alignment in stacked memory. The memory a number of core dice stacked on an interface die. The core and interface die each include adjustable delay circuits along each of a delay and native path. A state machine operates interface and core aligner control circuits to set values of the delay(s) in the interface and core dice respectively. The state machine may initialize the delays and then enter a maintenance state where averaging is used to determine when to adjust the delay in the core dice. If an overflow or underflow condition is met, the state machine may cycle between adjusting the delay in the interface die and adjusting the delays in the core dice without averaging until the overflow and underflow conditions are no longer met and the maintenance state is returned to.