Replacement Gate Transistor and NVM Integration Using High-k Dielectric
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a need to enhance the performance of integrated circuits that combine non-volatile memory (NVM) and logic functions while minimizing cost increases, particularly in the context of replacement gate technology, which uses a high-k dielectric to improve performance without sacrificing logic performance.
Innovation Solution
The integration of a replacement gate transistor and a non-volatile memory cell involves forming a charge storage layer, a dummy gate, and an interlayer dielectric, with the interlayer dielectric being removed from the NVM portion while retained in the logic portion, and a high-k dielectric is formed over the charge storage material and semiconductor material, enabling efficient formation of a control gate and logic gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If replacement gate technology is used to improve logic performance with high-k dielectric, then logic performance is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent combines the formation of replacement gate transistor and non-volatile memory cell into a single integrated process. The high-k dielectric layer is formed once and serves dual purposes: as the gate dielectric for the logic transistor and as the tunnel dielectric for the NVM cell, eliminating the need for separate formation processes and reducing overall manufacturing complexity.
Solution Approach 2:
The high-k dielectric layer performs multiple functions simultaneously: it acts as the gate dielectric for the logic transistor enabling high performance, and as the tunnel dielectric for the NVM cell enabling charge storage. This multi-functionality reduces the total number of layers and process steps required.
2Reliability
If high-k dielectric is formed over charge storage material in NVM portion, then NVM performance is improved, but process complexity increases
Solution Approach 1:
The high-k dielectric layer is formed in advance as part of the gate dielectric formation process before the NVM-specific processing steps. This preliminary formation of the high-k layer eliminates the need for subsequent dielectric deposition steps in the NVM region, simplifying the overall process.
Solution Approach 2:
The patent applies different processing sequences to different regions: in the NVM portion, the high-k dielectric is retained and processed as the tunnel dielectric, while in the logic portion, it is processed as the gate dielectric. This localized quality approach allows each region to be optimized independently while using the same base material layer.
3Adaptability or versatility
If interlayer dielectric is removed from NVM portion while retained in logic portion, then selective processing is enabled, but manufacturing difficulty increases
Solution Approach 1:
The patent segments the interlayer dielectric removal process by applying masks that selectively protect the logic portion while exposing the NVM portion for dielectric removal. This segmentation allows independent processing of different device types on the same wafer, enabling customization without increasing overall manufacturing difficulty.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for improved performance and cost-effectiveness by efficiently integrating high-k dielectric materials in both NVM and logic regions, enhancing the performance of integrated circuits without increasing costs.
Implementation Method 1
a high-k dielectric is formed after removing a dummy gate so that the high-k dielectric is over the charge storage material and on a semiconductor material at a bottom of an opening left by the removal of the dummy gate
Data Source
AI summary
A first dielectric layer is formed in an NVM region and a logic region. A charge storage layer is formed over the first dielectric layer and is patterned to form a dummy gate in the logic region and a charge storage structure in the NVM region. A second dielectric layer is formed in the NVM and logic regions which surrounds the charge storage structure and dummy gate. The second dielectric layer is removed from the NVM region while protecting the second dielectric layer in the logic region. The dummy gate is removed, resulting in an opening. A third dielectric layer is formed over the charge storage structure and within the opening, and a gate layer is formed over the third dielectric layer and within the opening, wherein the gate layer forms a control gate layer in the NVM region and the gate layer within the opening forms a logic gate.