Metal Electrode Fabrication in CMOS Using Contact Metal
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Solution Overview
Problem
Conventional methods for fabricating metal capacitor/gate electrode structures in CMOS processes are complex and require additional steps, such as multiple metal layer deposition and chemical-mechanical polishing, which complicate the process flow and are not compatible with standard CMOS processes.
Innovation Solution
A method to fabricate metal electrodes with minimal modifications to the conventional single-poly CMOS process by forming a non-conventional mask over the pre-metal dielectric layer, etching grooves to expose polysilicon structures, depositing a dielectric layer, and using a conventional contact process to form metal electrodes, which can be used as capacitor plates or gate electrodes without altering the existing process flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional methods are used to fabricate metal capacitor/gate electrode structures, then metal electrodes can be formed, but the process complexity increases significantly due to multiple metal layer deposition and chemical-mechanical polishing steps
Solution Approach 1:
The patent combines the formation of metal capacitor electrodes and metal gate electrodes into a single integrated process flow. The contact metal deposition step simultaneously forms both the capacitor upper electrode in the capacitor groove and the metal gate electrode in the transistor region, eliminating the need for separate deposition and polishing processes that would otherwise be required.
Solution Approach 2:
The contact metal deposition process serves multiple functions: it forms the upper capacitor electrode, forms the metal gate electrode, and provides electrical connectivity. This multi-functional approach replaces conventional processes that would require separate steps for each function, thereby reducing overall process complexity.
2Adaptability or versatility
If additional metal layers are deposited prior to polysilicon layer, then metal gate electrodes can be formed, but the CMOS process flow is significantly complicated
Solution Approach 1:
The patent performs preliminary actions by forming the capacitor groove and isolating the polysilicon structure before the contact metal deposition. This allows the contact metal to be deposited directly as the gate electrode without requiring additional metal layers to be deposited beforehand, maintaining compatibility with standard CMOS process flows.
Solution Approach 2:
The dielectric layer serves as an intermediary that isolates the polysilicon structure from the contact metal. This intermediary layer enables the contact metal to function as a gate electrode while preventing direct contact with the polysilicon, thereby achieving metal gate capability without complicating the overall process flow.
3Adaptability or versatility
If control gate mask formation and etch steps are added, then EEPROM control gates can be formed, but the process complexity increases
Solution Approach 1:
The patent merges the control gate formation process with the existing contact formation process. The same contact mask and contact metal deposition steps that form contact plugs also form the EEPROM control gate, eliminating the need for separate control gate mask formation and etch steps.
Solution Approach 2:
The contact metal deposition process serves the dual function of forming both contact plugs and EEPROM control gates. This multi-functional approach reduces the total number of process steps while maintaining the ability to form EEPROM control gates with the desired characteristics.
Data Source
AI summary
A capacitor structure is fabricated with only slight modifications to a conventional single-poly CMOS process. After front-end processing is completed, grooves are etched through the pre-metal dielectric layer to expose polysilicon structures, which may be salicided or non-salicided. A dielectric layer is formed over the exposed polysilicon structures. A conventional contact process module is then used to form contact openings through the pre-metal dielectric layer. The mask used to form the contact openings is then removed, and conventional contact metal deposition steps are performed, thereby simultaneously filling the contact openings and the grooves with the contact (electrode) metal stack. A planarization step removes the upper portion of the metal stack, thereby leaving metal contacts in the contact openings, and metal electrodes in the grooves. The metal electrodes may form, for example, transistor gates, EEPROM control gates or capacitor plates.