Semiconductor Memory Extraction Section Area Reduction
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Solution Overview
Problem
The miniaturization of nonvolatile semiconductor memory devices using conventional floating gate technology is challenging, and the double patterning technology required for three-dimensional crosspoint cells in ReRAMs results in an exponential increase in area and complexity, making miniaturization difficult due to the large number of extraction sections needed.
Innovation Solution
The semiconductor memory device employs a damascene method and sidewall process to manufacture the extraction section, reducing the area required for contact regions and minimizing the number of exposures needed, allowing for a more compact and efficient layout by forming contact regions in a concave shape and using a spacer to determine the minimum processing dimension, thereby reducing the extraction section's area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double patterning technology is used to form three-dimensional crosspoint cells, then manufacturing precision is improved, but device complexity increases exponentially
Solution Approach 1:
The extraction section is divided into multiple extraction regions, with each region handling a specific set of interconnects. This segmentation allows the complex extraction function to be distributed across multiple simpler units, reducing overall device complexity while maintaining manufacturing precision through standardized repeating structures.
Solution Approach 2:
The patent transitions from planar extraction sections to three-dimensional extraction regions that extend vertically through multiple interconnect layers. This dimensional change allows interconnects from different layers to be extracted and connected in three-dimensional space, reducing the area required and simplifying the routing complexity compared to traditional planar approaches.
2Adaptability or versatility
If the number of extraction sections is increased to connect more interconnects, then connectivity is improved, but area increases exponentially
Solution Approach 1:
Extraction regions are nested within larger extraction sections, with multiple extraction regions sharing common contact structures and interconnect routing. This nesting allows the area required for connectivity to increase linearly rather than exponentially, as shared structures serve multiple functions across different extraction regions.
Solution Approach 2:
Contact structures and interconnect routing are designed to serve multiple extraction regions simultaneously. A single contact structure may connect interconnects from multiple layers to multiple extraction regions, providing universal connectivity that reduces the total area required compared to dedicated one-to-one connections.
3Ease of manufacture
If conventional floating gate technology is used, then manufacturing simplicity is maintained, but miniaturization capability deteriorates
Solution Approach 1:
The patent employs three-dimensional crosspoint cell structures with vertical stacking of memory cells and interconnects. This transition to three-dimensional architecture enables continued miniaturization by utilizing the vertical dimension, allowing higher storage density without requiring proportionally larger planar areas, thus maintaining manufacturing feasibility while achieving miniaturization.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a first interconnect, a second interconnect, a first fringe and a second fringe. The first interconnect is connected to a first memory cell. The second interconnect is connected to a second memory cell and is arranged at a first interval from the first interconnect in a first direction. The first fringe is formed on one end of the first interconnect. The second fringe is formed on one end of the second interconnect. The first fringe and the second fringe are arranged at the first interval in a second direction orthogonal to the first direction.