Pixel Metal Grid Openings for Electrical Substrate Contact
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Solution Overview
Problem
In back-illuminated CMOS image sensors, the metal grid formed in the pixel area is physically connected but not electrically connected to the underlying substrate and deep-trench fill structures, limiting the optimization of electrical performance.
Innovation Solution
A method is developed to fabricate a semiconductor device by forming a trench fill structure in the substrate, covering it with a buffer dielectric layer, etching to expose portions of the substrate, and creating a metal grid layer that fills these openings to establish electrical connection with the substrate and trench fill structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a buffer dielectric layer is used to separate the metal grid from the underlying substrate and trench fill structures, then physical connection is achieved, but electrical connection is lost
Solution Approach 1:
The patent removes the buffer dielectric layer from between the metal grid and the underlying substrate/trench fill structures, allowing direct electrical contact. This extraction of the insulating layer resolves the contradiction by eliminating the barrier to electrical connection while maintaining the physical separation function through alternative means.
Solution Approach 2:
The patent introduces an opening structure that penetrates through the buffer dielectric layer, serving as an intermediary pathway that allows electrical connection between the metal grid and the underlying structures while preserving the buffer layer's physical separation function in other areas.
2Reliability
If the metal grid is physically separated from the substrate by a buffer dielectric layer, then structural integrity is maintained, but electrical performance cannot be optimized
Solution Approach 1:
The patent applies local quality by creating localized openings in the buffer dielectric layer only where electrical connection is needed, while maintaining the buffer layer's physical separation function in other regions. This allows simultaneous achievement of electrical performance optimization and structural stability.
Solution Approach 2:
The patent transitions from a two-dimensional planar separation to a three-dimensional structure with vertical openings, allowing electrical connection in the vertical dimension while maintaining horizontal physical separation. This dimensional change resolves the contradiction between electrical and structural requirements.
3Reliability
If the buffer dielectric layer completely buries the trench fill structure, then manufacturing simplicity is achieved, but electrical connectivity is prevented
Solution Approach 1:
The patent performs preliminary action by forming the opening structure through the buffer dielectric layer before final metal grid deposition, allowing the buffer layer to be formed as a complete burying layer first, then selectively opened to achieve both manufacturing simplicity and electrical connectivity.
Solution Approach 2:
The patent segments the buffer dielectric layer by creating openings that divide it into regions with different functions: areas with openings for electrical connection and areas without openings for physical separation and manufacturing simplicity.
Data Source
AI summary
A method of fabricating of semiconductor device is disclosed. The method of fabricating semiconductor device includes: forming a trench fill structure in a substrate in a pixel area; covering a buffer dielectric layer over a surface of the substrate in the pixel area, the buffer dielectric layer burying the trench fill structure; etching the buffer dielectric layer to form a first opening, which at least exposes a portion of the substrate surrounding a top surface of the trench fill structure; and forming a metal grid layer on the buffer dielectric layer, wherein the metal grid layer fills the first opening to at least directly contact with and electrically connect to the exposed portion of the substrate. The present invention provides a technical solution that brings the metal grid layer into electrical connection with the exposed portion of the substrate, thus allowing optimization or amelioration of the semiconductor device's electrical performance.