Tapered Semiconductor Base for 3D Memory Pillar Strength
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Solution Overview
Problem
Memory devices with three-dimensionally arranged memory cells face challenges in increasing density without compromising mechanical strength, leading to semiconductor pillar damage during manufacturing and reduced yield.
Innovation Solution
A memory device design featuring a semiconductor base with a wider width at the portion extending through the second electrode layer and a narrower width connected to the semiconductor layer, along with a manufacturing process that includes forming a convex portion on the semiconductor base and using thermal oxidation to enhance mechanical strength and prevent damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of semiconductor members is reduced to increase density, then the memory capacity increases, but the mechanical strength decreases
Solution Approach 1:
The semiconductor base is designed with non-uniform width, being wider at the lower portion (first width) and narrower at the upper portion (second width). This local variation in geometry concentrates mechanical strength where needed (at the base) while allowing the upper portions to maintain smaller dimensions for high density. The different widths create a tapered structure that optimizes both strength and density requirements in different spatial locations.
2Quantity of substance
If the size of semiconductor members is reduced to increase density, then the memory capacity increases, but the manufacturing yield decreases due to pillar damage
Solution Approach 1:
The tapered geometry with wider base provides enhanced mechanical support at the critical lower portion where semiconductor members are most vulnerable during manufacturing. This local strengthening at the base reduces damage risk during processing while maintaining small dimensions at the upper portions for high density, thereby improving manufacturing yield without sacrificing density.
3Strength
If the width of semiconductor base is increased to improve mechanical strength, then the structural integrity improves, but the device area increases
Solution Approach 1:
The semiconductor base employs non-uniform width distribution, being wider only at the lower portion where mechanical strength is critical, and narrower at the upper portion. This localized widening provides the necessary structural support without increasing the overall device area, as the narrower upper portion maintains compact dimensions suitable for high-density integration.
Solution Approach 2:
Instead of uniformly increasing the base area in two dimensions, the invention utilizes the vertical dimension by creating a tapered structure with varying width through the thickness. This allows the base to have larger cross-sectional area at the lower portion for strength while maintaining smaller footprint at the upper portion, effectively using the third dimension to resolve the area-strength tradeoff.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design improves the mechanical strength of semiconductor members, reducing the likelihood of damage during manufacturing and enhancing the manufacturing yield by maintaining the structural integrity of the semiconductor pillars.
Implementation Method 1
a manufacturing process that includes forming a convex portion on the semiconductor base and using thermal oxidation to enhance mechanical strength
Data Source
AI summary
The memory device includes a conductive layer, a plurality of first electrode layers stacked over the conductive layer and spaced from each other in a first direction, a semiconductor layer extending through the first electrode layers in the first direction, a second electrode layer provided between the conductive layer and the first electrode layers, and a semiconductor base, located between the conductive layer and the semiconductor layer and extending through the second electrode layer, wherein the semiconductor base has a first width at a portion thereof extending through the second electrode layer in the first direction and second width at a portion thereof connected to the semiconductor layer, and the first width is greater than the second width.