Chip Floorplan Arrangement for IC Area and Thermal Efficiency

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Solution Overview

Problem

Current IC packaging technologies face issues such as wasted area, poor heat dissipation, and difficulty in wiring due to inefficient floorplan arrangements of chips, leading to uncompetitive products and increased manufacturing complexity.

Innovation Solution

A chip floorplan arrangement where multiple chips are strategically positioned in quadrants on a substrate or interposer, allowing for rotational symmetry and point symmetry, enabling efficient pin arrangement and simplified manufacturing by using the same photomask for different areas, thereby optimizing space and reducing pin waste.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If chips are arranged in a conventional floorplan layout, then the IC product can be manufactured, but the substrate area is wasted and the product size increases

Engineering Contradiction:

Improvesubstrate area utilizationVSAvoidproduct size

Core Design Contradiction:

Area of stationary objectVSLength of stationary object

Solution Approach 1:

The patent applies asymmetry by arranging chips in non-traditional positions that break conventional symmetric floorplan patterns. Chips are strategically placed to maximize substrate utilization while minimizing overall product footprint, creating an asymmetric layout that optimizes both area efficiency and size reduction

Inventive Principle:

Principle #4Asymmetry

2Area of stationary object

If chips are densely arranged to reduce area, then substrate area utilization improves, but heat dissipation performance deteriorates

Engineering Contradiction:

Improvesubstrate area utilizationVSAvoidheat dissipation

Core Design Contradiction:

Area of stationary objectVSTemperature

Solution Approach 1:

The patent applies local quality by creating different spatial zones with distinct characteristics. High-density chip regions are strategically positioned away from heat-sensitive areas, and thermal management resources are concentrated in specific locations where heat generation is highest, optimizing both area utilization and heat dissipation locally

Inventive Principle:

Principle #3Local quality

3Loss of substance

If chips are arranged with optimal positioning, then pin waste is reduced, but the complexity of achieving ideal relative positions increases

Engineering Contradiction:

Improvepin wasteVSAvoidfloorplan arrangement complexity

Core Design Contradiction:

Loss of substanceVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the substrate into distinct functional zones or regions, each with specific chip placement requirements. This modular approach simplifies the overall arrangement complexity by breaking down the floorplan design into manageable segments with standardized placement rules

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS11830850B2Integrated circuit product and chip floorplan arrangement thereof

Publication Date: 2023.11.28 ALCHIP TECH

AI summary

An integrated circuit product includes a first chip to a twelfth chip. The first to fourth chips are respectively arranged in a first quadrant, a fourth quadrant, a third quadrant, and a second quadrant of the integrated circuit product, and the first chip is adjacent to the second chip and the fourth chip. The fifth to eighth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the fifth to eighth chips are not adjacent to each other. The ninth to twelfth chips are respectively arranged in the first quadrant, the fourth quadrant, the third quadrant, and the second quadrant of the integrated circuit product, and any two of the ninth to twelfth chips are not adjacent to each other.