Vertical CBRAM Stack Sidewall Profile for Leakage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current crossbar arrays with conductive bridge random access memory (CBRAM) devices face challenges in minimizing leakage currents and power consumption due to half-select errors, which limit the size and efficiency of the arrays, especially during parallel operations and stochastic weight updates.
Innovation Solution
The formation of a vertical stack comprising a CBRAM device and an access device connected in series, utilizing subtractive etching to create a sidewall profile that increases in width from the bottom to the top, which helps in minimizing half-select errors by optimizing the voltage window and reducing leakage currents through the selection of appropriate materials for the CBRAM and access devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional crossbar arrays with CBRAM devices are used, then the array size can be increased, but leakage currents and power consumption increase due to half-select errors
Solution Approach 1:
The crossbar array is segmented into multiple layers with alternating conductive bridge random access memory (CBRAM) and access device layers. This segmentation allows for better control of leakage currents by dividing the array into manageable units with independent selection capabilities, reducing the impact of half-select errors on overall power consumption.
Solution Approach 2:
Access devices are introduced as intermediary elements between the row and column wires in the crossbar array. These access devices act as mediators that control current flow more precisely, enabling selective activation of CBRAM cells and minimizing leakage currents through unselected cells during parallel operations.
2Quantity of substance
If conventional crossbar arrays with CBRAM devices are used, then the array size can be increased, but half-select errors increase limiting efficiency
Solution Approach 1:
The array is divided into multiple layers with alternating CBRAM and access device structures. This segmentation enables more precise cell selection by requiring simultaneous activation of specific row and column lines within each layer, thereby reducing half-select errors and improving reliability as array size increases.
Solution Approach 2:
Access devices serve as intermediary control elements that enhance selection precision. By introducing these additional control points, the system can more accurately select target cells while preventing unintended activation of neighboring cells, thus reducing half-select errors in larger arrays.
3Loss of energy
If vertical stacks with subtractive etching are used, then leakage currents are minimized, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process employs periodic alternation of CBRAM and access device layer formations through repeated cycles of depositing and etching. This periodic action, implemented via subtractive etching, creates the vertical stack structure with alternating layers, enabling effective leakage current minimization while organizing the complex manufacturing steps into manageable periodic cycles.
Data Source
AI summary
A semiconductor structure comprises a conductive bridge random access memory device and an access device connected in series with the conductive bridge random access memory device. The conductive bridge random access memory device and the access device are arranged in a vertical stack. The vertical stack has a sidewall profile that increases in width from a bottom surface of the vertical stack to a top surface of the vertical stack.