Stacked Active-Layer Array Substrate for Longer TFT Channels
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Solution Overview
Problem
Current VR display technologies face stability issues due to short channel lengths of active layers in thin film transistors of array substrates, leading to poor device performance.
Innovation Solution
The solution involves an array substrate design with a stack of first and second active layers and metal layers, where the drain region of the first active layer is electrically connected to the source region of the second active layer, increasing the channel length of drive transistors without expanding their area on the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel length of active layers is increased to improve device stability, then the device stability is improved, but the occupied area on the substrate increases
Solution Approach 1:
The patent applies dimensionality change by stacking active layers vertically in the thickness direction to extend the channel length. Instead of extending the channel horizontally which would increase occupied area, the invention stacks multiple active layers (first active layer and second active layer) vertically, each with its own channel region, thereby increasing the effective channel length in the vertical dimension while maintaining a compact horizontal footprint on the substrate.
Solution Approach 2:
The patent implements nesting by placing the second active layer on top of the first active layer, with the first gate electrode positioned between them. The structures are nested vertically where the second active layer is disposed on the first metal layer which is on the first active layer, creating a compact stacked configuration that increases channel length without proportionally increasing the occupied area.
2Reliability
If multiple active layers are stacked to increase channel length, then device stability is improved, but the device complexity increases
Solution Approach 1:
The first gate electrode serves multiple functions simultaneously: it controls both the first active layer and the second active layer, and also acts as a shielding layer to reduce interference between the two active layers. This multi-functionality reduces the need for additional separate control structures, thereby limiting the increase in device complexity despite stacking multiple active layers.
Solution Approach 2:
The patent merges the gate control function and the shielding function into a single first gate electrode structure. By combining these functions into one element rather than using separate structures, the invention reduces overall device complexity while still achieving the goal of increased channel length and improved stability through vertical stacking.
Data Source
AI summary
An array substrate, a display panel, and a display terminal are provided. The array substrate includes: a substrate; a first active layer disposed on the substrate; a first metal layer including a source electrode electrically connected to one end of the first active layer and a first gate electrode disposed opposite to the first active layer; a second active layer disposed on the first metal layer and electrically connected to the first active layer, wherein, the first gate electrode is disposed opposite to the second active layer; and a second metal layer including a drain electrode electrically connected to the second active layer.