Interlaced String Select Structures for 3D NAND Array Efficiency
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Solution Overview
Problem
Current 3D memory devices face challenges in achieving high array efficiency and improved on/off characteristics due to the use of multiple sets of string select structures and ground select lines, which reduce performance.
Innovation Solution
The semiconductor device employs interlaced string select structures acting as side gates for active strips, with control circuitry applying specific voltages to select and unselect memory cells, optimizing the arrangement of string select structures and ground select lines to enhance array efficiency and current control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two sets of SSL gate structures and two horizontal ground select lines are used, then ground select functionality is provided, but array efficiency is reduced
Solution Approach 1:
The patent combines two separate ground select line structures into a single shared ground select line that serves both sets of active strips. This merging reduces the total number of ground select lines from two to one, thereby improving array efficiency while maintaining the required ground select functionality for both sets of NAND strings.
2Reliability
If two sets of ground contacts are used, then ground connection is provided for both sets of active strips, but device complexity increases
Solution Approach 1:
The patent merges two separate ground contact structures into a single shared ground contact that provides ground connection for both sets of active strips. This reduces the total number of ground contacts from two to one, simplifying the device structure while maintaining reliable ground connections for all active strips.
3Ease of manufacture
If string select structures are positioned at the same location, then manufacturing is simplified, but on/off characteristics deteriorate
Solution Approach 1:
The patent employs asymmetric positioning of string select structures, where first and second string select structures are positioned at different locations relative to the active strips. This asymmetric arrangement creates distinct electrical pathways that improve on/off characteristics by better controlling the selection of individual active strips, while the positioning remains manufacturable.
Solution Approach 2:
The patent applies different positioning configurations to different string select structures based on their local requirements. First string select structures are positioned at one location optimized for their function, while second string select structures are positioned at a different location optimized for their function, allowing each structure to have optimal local characteristics.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves array efficiency and differentiates ON and OFF states effectively, resulting in better current control and performance compared to existing technologies.
Implementation Method 1
The string select structures are configured to act as side gates for channels in the active strips, thereby forming string select switches
Data Source
AI summary
A semiconductor device includes a plurality of active strips, where active strips in the plurality are coupled together at one end by a pad and terminated at another end by a conductive line. The device includes memory cells at cross-points between the plurality of active strips and a plurality of word lines. The device includes string select structures arranged in an interlaced configuration as side gates for active strips. The device includes control circuitry, configured to turn on a particular active strip by applying a turn-on voltage to two string select structures arranged as side gates for the particular active strip, and to turn off a second particular active strip by applying a turn-off bias to at least one string select structure arranged as a side gate for the second particular active strip. The turn-off bias includes one of a ground voltage, a non-negative voltage, and a floating condition.