3D Stacked Circuit Units With Vertical Buses for Shorter IC Wiring
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Solution Overview
Problem
Wires in integrated circuits (ICs) dominate performance, functionality, and power consumption as they degrade with scaling, necessitating innovative solutions to reduce wire lengths and improve connectivity.
Innovation Solution
The development of 3D stacked integrated circuits using layer transfer technologies that support the reuse of donor wafers and fabrication of active devices on transferred layers, incorporating vertical data and control lines to provide electrical connections between multiple circuit levels, including oxide-to-oxide and metal-to-metal bonding regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scaling is used to increase functionality and performance, then transistor density improves, but wire performance degrades and power consumption increases
Solution Approach 1:
The patent transitions from 2D planar integration to 3D stacked architecture, organizing transistors and interconnects in vertical layers. This dimensional change allows transistors to be placed closer in the vertical dimension while reducing horizontal wire lengths, thereby improving transistor density without proportionally increasing wire length and power consumption
2Productivity
If scaling is used to increase functionality and performance, then transistor density improves, but wire length increases and wiring delay increases
Solution Approach 1:
By stacking multiple transistor layers vertically, the patent reduces the horizontal distance electrons must travel between transistors. The vertical interconnects (through-silicon vias) provide direct short-path connections between layers, significantly reducing overall wire length compared to 2D lateral routing
Solution Approach 2:
The patent divides the integrated circuit into multiple stacked layers, each containing transistors and interconnects. This segmentation allows independent optimization of each layer and reduces the complexity of long-distance wiring by localizing connections within and between adjacent layers
3Speed
If 3D stacking is used to reduce wire lengths, then wiring delay decreases, but device complexity increases
Solution Approach 1:
The patent implements a hierarchical nested structure where multiple complete circuit layers are stacked and interconnected. Each layer is a self-contained unit that can be designed and manufactured separately, then integrated into the 3D stack, managing complexity through modular nesting
Data Source
AI summary
A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors, the second level overlaying the first level; and at least four electronic circuit units (ECUs), where each of the ECUs include a first circuit, the first circuit including a portion of the first transistors, where each of the ECUs includes a second circuit, the second circuit including a portion of the second transistors, where each of the ECUs includes a first vertical bus, where the first vertical bus provides electrical connections between the first circuit and the second circuit, where each of the ECUs includes at least one processor and at least one memory array, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonding regions and metal to metal bonding regions.