3D Circuit Structure Waterproof Encapsulation

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Solution Overview

Problem

Conventional 3D circuit structures are vulnerable to moisture, dust, scratches, and peeling, leading to unstable electrical characteristics and non-compliance with safety codes for electrical insulation due to exposed metal conducting traces without adequate protection.

Innovation Solution

A 3D circuit structure featuring a 3D insulating substrate with a circuit trace layout layer and an insulating encapsulation member that covers the circuit forming zone, providing waterproof, dustproof, scratch-resistant, and secure characteristics while ensuring compliance with safety codes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If metal conducting traces are exposed on the carrier surface for 3D circuit formation, then circuit functionality is achieved, but the circuit becomes vulnerable to moisture, dust, scratches, and peeling

Engineering Contradiction:
Improveelectrical characteristic stabilityVSAvoidmoisture, dust, scratch exposure
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies a thin film encapsulation layer that conformally covers the 3D circuit structure, including vertical walls and horizontal surfaces. This flexible thin film provides comprehensive protection against moisture, dust, and scratches while maintaining the 3D circuit's electrical functionality and geometric complexity.

Inventive Principle:
Principle #30Flexible shells and thin films

Solution Approach 2:

The patent employs composite material structures combining the carrier substrate, metal conducting traces, and protective encapsulation layers. This multi-material composite approach enables simultaneous achievement of electrical conductivity, mechanical protection, and environmental resistance in the 3D circuit structure.

Inventive Principle:
Principle #40Composite materials

2Reliability

If metal conducting traces are formed on the carrier surface, then circuit connectivity is established, but adhesion is poor and traces tend to peel off

Engineering Contradiction:
Improvetrace adhesionVSAvoidtrace-to-carrier bonding strength
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

The patent implements localized adhesion enhancement through specific surface treatments or adhesion promoter layers applied only at the interface between metal traces and carrier. This local quality modification improves trace-to-carrier bonding strength precisely where needed without affecting other circuit properties.

Inventive Principle:
Principle #3Local quality

3Reliability

If metal conducting traces are exposed to open space, then circuit functionality is maintained, but safety code compliance for electrical insulation is failed

Engineering Contradiction:
Improveelectrical insulation safetyVSAvoidinsulation structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent uses thin film encapsulation to provide electrical insulation for exposed metal traces in 3D circuit configurations. This approach ensures safety code compliance while maintaining the compact 3D structure without requiring complex external insulation housings or enclosures.

Inventive Principle:
Principle #30Flexible shells and thin films

Data Source

PatentUS10522533B1Three-dimensional circuit structure
Publication Date: 2019.12.31 PIN SHINE INDAL
  • US10522533B1 patent drawing
  • US10522533B1 patent drawing
  • US10522533B1 patent drawing

AI summary

A three-dimensional (3D) circuit structure includes a 3D insulating substrate having at least one circuit forming zone and at least one exposed contact forming zone; at least one circuit pattern portion provided on the 3D insulating substrate and having at least one circuit trace layout layer located in the circuit forming zone and at least one exposed contact located in the exposed contact forming zone and connected to the circuit trace layout layer; and an insulating encapsulation member covering at least the circuit forming zone and the circuit trace layout layer. With the insulating encapsulation member, the circuit trace layout layer is waterproof, dustproof, scratch-resistant, peeling-proof, secure for use, and compliant with safety codes of electrical insulation, enabling the 3D circuit structure in use to have stable electrical characteristics.