3D Monolithic CMOS Image Sensor for In-Memory AI Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current AI CMOS image sensors face challenges with complex package processes, high power consumption, and limited miniaturization due to the need for multiple heterogeneous substrates and DRAM-based storage, which complicates integration and increases thickness, making them unsuitable for advanced applications like AI and edge computing.
Innovation Solution
A 3D monolithic CMOS image sensor architecture that integrates oxide-semiconductor field effect transistors (OSFETs) and ferroelectric metal-insulator-metal (FEMIM) capacitors directly on BEOL metal layers, eliminating the need for wafer bonding and TSVs, and enabling in-memory computing with reduced thickness and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If 3D package and wafer-level bonding are used to integrate memory and logic circuits, then component integration is achieved, but device thickness increases and reliability decreases
Solution Approach 1:
The patent merges memory and logic circuits onto a single substrate using CMOS-compatible processes, eliminating the need for separate 3D packaging and wafer bonding operations. This integration approach consolidates multiple components into one unified structure, reducing overall device thickness while maintaining full functionality.
Solution Approach 2:
The patent employs a universal substrate that can accommodate both memory and logic circuit fabrication using standard CMOS processes. This multi-functional substrate design allows diverse components to be integrated without requiring specialized packaging structures, thereby reducing device thickness.
2Adaptability or versatility
If 3D package and wafer-level bonding are used to integrate memory and logic circuits, then component integration is achieved, but manufacturing complexity and reliability issues increase
Solution Approach 1:
The patent combines memory and logic circuit fabrication into a single manufacturing process flow on one substrate, eliminating complex 3D packaging steps and wafer bonding operations. This unified approach simplifies the overall manufacturing process while achieving complete component integration.
Solution Approach 2:
The patent uses homogeneous CMOS-compatible processes for fabricating both memory and logic circuits on the same substrate. This homogeneous manufacturing approach eliminates the need for heterogeneous packaging processes, reducing manufacturing complexity and improving reliability.
3Quantity of substance
If DRAM is used as storage unit with repeated data transmission between computing unit and memory, then storage functionality is provided, but power consumption increases
Solution Approach 1:
The patent merges storage and computing functions onto a single integrated substrate, enabling in-memory computing operations. This eliminates the need for repeated data transmission between separate memory and computing units, significantly reducing power consumption while maintaining storage capacity.
Solution Approach 2:
The patent enables continuous computation within the storage structure itself, allowing data to be processed directly where it is stored without repeated read-write cycles. This continuous operation mode eliminates idle transmission periods and reduces overall power consumption compared to traditional DRAM architectures.
Data Source
AI summary
A CMOS image sensor with 3D monolithic OSFET and FEMIM capacitor, including a substrate with CMOS devices formed thereon, a BEOL interconnect layer on the substrate and with BEOL interconnects formed therein, a pixel circuit layer on the BEOL interconnect layer. The OSFETs and FEMIM capacitors are formed in the pixel circuit layer, and a photoelectric conversion layer on the pixel circuit layer and with photodiodes are formed therein, wherein the CMOS devices, the OSFETs, FEMIM capacitors and photodiodes are electrically connected with each other through the BEOL interconnects.