Solid-State Devices TRIZ Cases

Horizontal coupling of RGB LED units cuts pixel mounting count, avoids electrode light blockage, and improves color mixing and contrast.

An inkjet-formed metal bridge links auxiliary and counter electrodes to cut voltage drop and protect flexible display image quality.

Adding metal such as lanthanum into the CMOS isolation region reduces local layout effect and stabilizes transistor threshold voltage.

Separating light-emitting and circuit areas helps inorganic LED displays improve durability, blue efficiency, and manufacturing alignment.

A DABNA-based polycyclic compound in the emission layer boosts OLED emission efficiency and supports longer element lifespan.

Temperature-tuned bonding and support layers distribute bending stress so foldable displays recover flatness and resist crease damage.

By merging light shielding, source, and drain layers with simultaneous via etching, this case simplifies array substrate fabrication and improves contact reliability.

Varying gate, barrier, and channel parameters enables GaN HEMTs with different threshold voltages on one IC, cutting parasitics, power, and size.

MicroLED and photodetector stacks replace electrical chip links to raise interconnect density while cutting power in 2.5D and 3D ICs.

A doped body-to-source ohmic path drains channel holes in PD-SOI transistors, removing kink effect without a separate body terminal.

Stacked logic dice linked by direct bonding, through-array vias, and contacts cut peripheral area while improving bit density and memory performance.

Patterned reflective layers and staged microdevice transfer improve bonding yield, light uniformity, and integration cost on optical display substrates.

Close-packed heterogeneous dies with 0-20 μm spacing use build-up layers and plated metal heat paths to cut latency while managing heat.

Parity and connection contact dielectric layers improve electrical properties and production yield in highly integrated semiconductor structures.

MicroLED optical links relocate memory away from the processor to expand capacity and ease thermal limits without losing bandwidth.

Auxiliary light-emitting elements and a color conversion layer replace defective pixel emitters without rework, preserving substrate use and display function.

A transparent buried electrode lets more incident light reach the photodetector while preserving LED emission efficiency in a stacked pixel.

Side reflective layers on adjacent color LEDs block lateral light mixing, improving color purity and display quality in dense panels.

Patterned protective-layer openings connect transferred microdevices to backplane circuits, cutting integration time while improving bonding yield.

An oxide semiconductor transistor paired with a capacitor stores data without power, avoiding refresh, high voltage, and write-endurance limits.

Groove-defined precursor growth and vapor conversion form stable perovskite micro-arrays without photoetching or ink-jet damage.

Inclined sidewalls, rounded corners, and controlled lead-frame gaps reduce wire breakage and encapsulant cracking in optoelectronic packages.

Different effective gate voltages across the TFT channel raise s-factor for gray scale while preserving strong ON-current in displays.

A layered carrier and distributor fluid path cools LED curing modules evenly, enabling stable UV ink and varnish curing with lower circuit complexity.

A roughened wafer backside enables low-load crack initiation before cleaving, cutting residual stress, dicing cost, and thermal-stress failures.

A support layer on the substrate side surface limits sharp electrode bending, cutting disconnection risk while keeping the bezel narrow.

A wider-bandgap barrier layer and integrated Zener clamp stabilize GaN transistor operation and improve reliability under high voltage and heat.

Bonding the light guide to a stretchable substrate through layer openings helps prevent pixel misalignment and preserve screen resolution.

Preformed partition walls and banks guide subminiature LEDs, cutting mask count while preventing short-circuits and display defects.

Backside power and signal routing with feed-through vias frees frontside area, cuts IR drop, and improves analog mismatch uniformity.

Series-biased PFETs beside a trench isolation region block cross-voltage leakage in multi-voltage ICs while preserving transistor performance.

Separating transistors and signal lines from the emission area enables bezel-less tiled displays while preserving color conversion and light transmission.

Preformed align keys and non-overlapping mold layers improve alignment precision and reliability in 3D stacked semiconductor storage.

Laser-cut grooves and tension-based wafer separation create a strengthened sidewall heat-affected zone that reduces chip cracking, kinking, and peeling.

A peripheral gate resistor layout diverts part of JFET gate-drain capacitance to cut switching overshoot and EMI without slowing dV/dt.

A Zener diode and detection electrode stabilize voltage in a power transistor structure, improving high-temperature reliability under high voltage.

Holding sheets enable batch alignment and joining of chip regions, cutting stacking steps and reducing breakage risk during multilayer device fabrication.

A TRSOI substrate with high-resistivity (111) silicon and low oxygen content cuts second harmonic distortion while preserving RF isolation.

Rotating the bonded substrate lets a blade form segmented circumferential grooves beyond its own length, improving separation efficiency and reducing damage.

Low-temperature BEOL oxide semiconductor NOT-gate stacks raise integration density and computing power without harming existing FEOL and MEOL devices.

A protruding electrode over the insulating sidewall enlarges the bonding interface, enabling reliable transfer of micrometer-scale emitters to substrate wiring.

Varying mask hole ratios tunes epitaxial growth and wavelength in sub-pixels, enabling smaller full-color LED units for high-definition displays.

A two-layer PSR structure masks interconnections while keeping pad openings clear, reducing micro LED bonding failures and improving black display quality.

Bridge patterns and aligned sidewalls improve micro LED electrode connection reliability while supporting miniaturized, high-efficiency integration.

Openings in the substrate and adhesive layer guide chip bonding and alignment, reducing tiling gaps and image discontinuity.

Specific host-dopant energy levels prevent iridium-free dopant decomposition, lowering OLED voltage while improving luminance and lifespan.

Segmented anodes localize current and isolate defective LED pixel regions, improving monolithic array yield and reducing repair complexity.

Self-aligned micro-LED placement with reflective electrodes and a surrounding conductive pattern reduces defects and improves light emission.

RGB-emitting LED stacks remove the color filter and pad alignment burden, improving yield and color quality in fine-pitch LEDoS microdisplays.

Vertical RGB LED stacks bypass selected emitters to remove color filters, improving microdisplay color quality, yield, and fine-pixel production.

Ferroelectric sidewall lining in stacked 3D memory openings cuts parasitic capacitance and energy use while supporting dense memory arrays.

A reflective film redirects UV to cure the quantum dot emission layer more fully and reduce interface mixing in the display stack.

Vertical stacking of memory cells with direct conductor contact boosts memory density while avoiding extra electrodes and added layout complexity.

Separate common voltages for OLED/QLED and Micro-LED subpixels improve display uniformity, efficiency, lifetime, and production cost.

A hump-shaped support member and clip stabilize lens bonding by limiting glue shift and preventing detachment under high temperatures.

Sidewall-mounted emitters on convex interlayers expand light-emitting angles, helping 3D display panels achieve a wider viewing range.

Varying black matrix hole sizes near transfer-area boundaries reduces side-angle stains and luminance differences without extra compensation.

A split pixel electrode layout with serial-parallel light emitting elements cuts off failures and improves light output efficiency.

Overlapping emission from segmented light sources boosts irradiation intensity while limiting LED junction temperature and mode complexity.

Opposed mesa orientation in selected pixels compensates LED asymmetry, reducing angle-dependent brightness change and color shift.

A vertical channel, surrounding common source line, and lower bit line simplify 3D memory integration while reducing process complexity.

Segmented pixel electrodes and laser cutting isolate defective light-emitting elements to prevent dark spots and preserve luminous efficiency.

Different metal doping regions plus a diffusion barrier raise selector ratio and suppress sneak leakage in dense cross-point memory arrays.

Sequential edge cuts on bonded wafers reduce trimming stress, chipping, and flaking while preserving thin 3DIC wafer stack integrity.

A dark encapsulation layer around LED chips absorbs ambient light reflection, improving display contrast and daylight visibility.

A tuned green and dual-red phosphor mix converts blue LED light into white light with higher efficiency, CRI, and R9 while limiting defects.

Bonded insulating layers and electrodes connect the LED pixel array to the driving circuit to improve uniform light emission across the display area.

By combining the active part and pixel electrode in one oxide layer, this panel structure cuts mask steps and lowers display backplane cost.

Overlapping the data line with a bridged voltage line cuts opaque wiring area, raising aperture ratio and transmittance in transparent displays.

Different well doping concentrations and bottom profiles cut parasitic capacitance in ESD protection, reducing RF signal loss without extra process steps.

Using front and back wiring layers, an island power tap cell cuts routing burden, shortens wire paths, and reduces parasitic impact in dense ICs.

Stacked color filters in non-emitting regions raise optical density to cut external light reflection while preserving thin, flexible display layouts.

A UV-to-violet LED with blue and YAG phosphors improves long-term luminous flux stability while preserving high color rendering and reducing blue light hazards.

A monolithic diode in parallel with the MOSFET body diode lowers tunable forward voltage drop to improve switching speed and efficiency.

Vertical LEDs are transferred onto pixel circuits and side-connected to exposed electrodes, cutting display thickness and improving moisture resistance.

By redirecting LED output through side surfaces, this backlight layout improves uniformity and blackout control in thinner LCDs.

An integrated photonic die, optical coupler, and lens structure improve optical coupling while avoiding copper-channel attenuation and crosstalk.

Laser-formed annular separation and expand tape remove the wafer edge before grinding, reducing debris smear and grinding stone damage.

Bridge electrodes lower contact resistance between pixel electrodes and light emitting elements, reducing dark spots and improving display performance.

A hydrophilic-hydrophobic stepped bank guides solution drying to flatten OLED emission layers and improve light emission efficiency.

Alternating two light-emitting groups by time division cuts directional interference and image crosstalk while preserving stereoscopic display quality.

Ion implantation partitions the LED active layer into light-emitting regions, improving resolution and refresh rate while reducing etching defects.

Dual bonding areas with solder and conductive adhesive enable micro LED replacement after transfer errors, reducing defective pixels.

An elevated element mount area lets a light receiver detect core leakage more sensitively while avoiding cladding contact and deformation.

A shared electrode doubles as a protective film over memory cells, cutting noise while supporting dense integration and stable transistor behavior.

Parasitic capacitance and a resistor form an RC trigger that turns on a main transistor during ESD, protecting ICs while saving area.

A segmented contact layout separates bonding and extension paths to improve LED current spreading without blocking light output.

Different insulating layer heights in micro-LED pixel areas block first-second electrode shorts from transfer misalignment and improve light efficiency.

Integrates nonvolatile memory into BCD IC fabrication using existing implant and anneal steps, adding only one mask while preserving density.

Scatterers in a layered light structure boost external light reflection and light emission efficiency without overly complex panel design.

By moving the binding region behind and overlapping the display area, this panel layout narrows splicing seams and preserves image continuity.

Independent control of conductive layers lets multi-quantum-well LEDs emit different wavelengths without phosphors, improving color accuracy.

An oxygen-deficient doped perovskite protective film shields lower electrodes during high-temperature dielectric deposition, preserving conductivity and crystal structure.

A low-temperature inorganic bond layer with aligned cavities protects heat-sensitive layers while preserving light output and assembly strength.

Visible-light LEDs with sub-500 ps response enable wireless links above 20 Gbps for uncompressed 4K and 8K video with lower power use.

Overlapping sub-pixels in repeated OLED pixel groups shorten spacing to improve display effect while simplifying mask openings and vapor deposition.

Doping the OLED P-type charge generation layer with 1% to 20% hole transport material improves hole injection, lowers voltage, and extends lifespan.

A horizontal-vertical S/D contact reaches the blocked bottom transistor, enlarging contact area and lowering resistance in stacked structures.

Metal partition openings guide inkjet-formed color conversion layers, improving placement stability and supporting high-resolution displays.

A protruding boundary buffer with deep and shallow trenches isolates mixed-voltage regions, reducing interference, yield loss, and process mismatch costs.

Polydisperse inorganic fillers in a high-solid phosphor layer improve pc-LED thermal stability, crack resistance, and long-term reliability.

Varying rear-side pixel isolation depths relieves substrate stress, suppresses line-shaped cracks, and preserves electrical isolation.

Parallel electrode bars and slits stabilize transmittance during low-frequency driving, reducing flexoelectric flicker in LCD sub-pixels.

A hydrogen-containing insulation portion in the connection region improves memory-cell passivation, density, and manufacturability.

Varying switching element counts and channel widths across sensing lines improves common voltage recovery and reduces display mura.

A side-surface light shielding film and annular frame block light leakage and crosstalk while avoiding coating cracks under thermal stress.

Delay adjustment circuits and symmetric wiring keep pixel timing and phase stable under power and ground fluctuations, improving TOF depth accuracy.

Electroless metal plating levels image sensor pad openings, enabling void-free glue bonding and reliable connections to transmissive covers.

Stacked optical layers split incident light into bands and guide more energy to photodiode regions, reducing filter loss in image sensors.

Two-stage recesses let fluid-transferred electronic units be detected and repositioned for accurate placement, stronger connections, and higher yield.

A protective pattern under the color control layer cuts reflection losses while protecting light-emitting elements in a thinner display stack.

Using light-emitting elements in both islands and bridges expands emission area, boosting display light output while limiting alignment complexity.

A low-hydrogen interface protection layer blocks radical attack during silicon nitride deposition, preserving electrode flatness and transmittance.

A through-hole organic layer structure improves pixel aperture while reducing light leakage and uneven topography in high-resolution displays.

Customized photodiode and LED angular filtering helps a touch display reject water-induced false touches while preserving accurate finger detection.

Intersecting conductive layers and vias embed an NFC antenna into the display substrate, saving module space without harming display uniformity.

Monolithic GaN integration of laterally terminated LEDs generates different colors on one substrate, cutting display fabrication complexity and cost.

Strategic first and second spacer placement strengthens low-PPI display panels against pressure, preventing black spots and Mura defects.

A backside interposer moves controller-die heat toward the package exterior while keeping a thin semiconductor assembly and coplanar contacts.

Differentiated backside source-drain access enables self-aligned contacts, lower power resistance, and smaller IC cell heights.

Separate guard rings around diode fingers cut capacitance loading and current crowding, improving ESD robustness in high-speed IC I/O.

Separate stacked wiring paths for brightness and event pixels enable faster event readout, lower power use, and higher image frame rates.

An insulating pattern between dual transfer gate poles reshapes the electric field to curb charge backflow and improve CMOS image sensor transfer.

A concave, inclined light-receiving surface helps shared-microlens pixels detect light direction and phase difference more accurately for autofocus.

Varying cell row heights and nanoribbon widths cuts wasted gate area and parasitic capacitance to improve IC switching and PPA.

A split RC IGBT chip separates IGBT-only and reverse-conducting regions to control bidirectional current while cutting on-state loss and thermal stress.

Integrated inter-die and intra-die vias shorten signal transfer paths in stacked optical chips, reducing sensor complexity, energy use, and yield loss.

Stacking the control circuit on a three-color LED structure cuts display area, avoids transfer bonding issues, and improves resolution.

Individual focusing optics for dislocated RGB LEDs control emission angles, limiting light displacement and improving display uniformity.

A staggered via arrangement lets adjacent unit cells sit closer together while reducing parasitic effects, dead space, and PPA loss.

A protrusion on the light-transmissive member strengthens substrate bonding, reduces peeling, and preserves light extraction in LED packages.

Overlapping contact holes and a transfer pad increase drain-to-pixel electrode contact area, lowering resistance in high-resolution displays.

Multiple light-emitting layers and segmented connection electrodes raise pixel density, boost luminance, and limit light leakage.

Separate power systems and substrate-level wiring densities curb heat and voltage fluctuation during neural processing, protecting image quality.

Using SiOCN sidewall spacers in RF switches cuts parasitic capacitance, leakage, and insertion loss while improving etch-back control.

Grooved insulation and via-based fanout route display wiring vertically, removing the bending region and shrinking bezel width.

Linear LED chip and lens layouts improve wide-angle visibility and color mixing, while body features strengthen encapsulant adhesion for moisture protection.

A dielectric-covered secondary electrode structure protects large-area OLED light-emitting regions from shorts while preserving emission uniformity.

A single-pixel layout combines SPAD sensing, filter gaps, and photodiodes to deliver proximity sensing and classical imaging on one chip.

Peripheral photopolymerization raises edge viscosity in ink-jetted quantum dot pixels, suppressing coffee rings and improving layer uniformity.

Separating light-emitting elements and TFT arrays onto different substrates improves material compatibility, connection space, yield, and cost.

A thermoelectric module between the sensor chip and cover plate transfers heat to suppress condensation while preserving image quality and transmittance.

A main support partly surrounds contact electrodes in the gate stack to keep etching uniform, improving memory reliability, productivity, and capacity.

Mode-controlled through-via switching lets stacked memory match different pin counts and transfer rates while reducing bump and packaging cost.

Relay electrodes and temporary-substrate wiring help fine-pitch micro LEDs connect to existing display electrodes without redesign.

Magnetic bodies in mold grooves improve LED transfer completeness, reduce mold damage, and cut repair steps in display assembly.

MicroLEDs, waveguides, and substrate photodetectors are integrated on ICs to cut chip-to-chip latency and power beyond electrical interconnect limits.

A platinum-based OLED layer expands the recombination zone to cut efficiency roll-off, lower driving voltage, and extend lifespan.

A three-layer dielectric ARC bends incident light toward a germanium image sensor element to cut reflection, limit cross-talk, and raise quantum efficiency.