3D Memory Channel and Source-Line Layout for Easier Integration
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Solution Overview
Problem
The manufacturing process of three-dimensional semiconductor memory devices is complex compared to two-dimensional devices, due to the intricate arrangement of memory cells.
Innovation Solution
A semiconductor memory device is designed with a substrate having a CMOS circuit, a gate stack structure with interlayer insulating layers and conductive patterns, a channel structure with a first part penetrating the gate stack and a second part extending beyond it, a common source line overlapping with the gate stack, a memory layer between the channel and gate stack, and a bit line connected to the channel structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are three-dimensionally arranged to improve integration, then the degree of integration is improved, but the manufacturing process complexity increases
Solution Approach 1:
The device is divided into distinct functional modules: gate stack structures (with interlayer insulating layers and conductive patterns), channel structures (with first and second parts), memory layers, bit lines, and common source lines. This segmentation allows each component to be manufactured and optimized independently, reducing overall manufacturing complexity while maintaining high integration
Solution Approach 2:
The patent transitions from two-dimensional planar arrangements to three-dimensional vertical stacking. Gate stack structures are stacked vertically with channel structures penetrating through them, and memory layers positioned between channel and gate components. This vertical dimension enables higher integration density without proportionally increasing manufacturing process complexity
2Adaptability or versatility
If a channel structure penetrates the gate stack structure with an extended part, then connectivity and integration are improved, but the structural complexity increases
Solution Approach 1:
The channel structure is designed with a first part that penetrates through the gate stack structure and a second part that extends beyond it, creating a nested configuration where the channel structure integrates multiple functional regions. The memory layer is positioned between the channel structure and gate stack, creating another nested arrangement that enables efficient connectivity while managing structural complexity
Data Source
AI summary
There is provided a semiconductor memory device including: a substrate having a Complementary Metal Oxide Semiconductor (CMOS) circuit; a gate stack structure including interlayer insulating layers and conductive patterns, which are alternately stacked in a vertical direction on the substrate; a channel structure having a first part penetrating the gate stack structure and a second part extending from one end of the first part, the second part extending beyond the gate stack structure; a common source line extending to overlap with the gate stack structure, the common source line surrounding the second part of the channel structure; a memory layer disposed between the first part of the channel structure and the gate stack structure; and a bit line connected to the other end of the first part of the channel structure, the bit line being disposed between the substrate and the gate stack structure.