Analog CMOS Cell Layout With Backside Power Rails for IR Drop
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Solution Overview
Problem
Analog circuit designs face issues with routing area shortages and large IR drops due to frontside signal and power/ground delivery, which can be exacerbated by feed-through via insertion and high cut metal gate density.
Innovation Solution
Implementing a super power rail structure with backside signal and power routing using feed-through vias and backside vias, along with a dual cut metal gate process to avoid area penalties and improve parasitic resistance uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If frontside routing is used for signal and power delivery, then routing is simplified, but routing area is insufficient and IR drop increases
Solution Approach 1:
The patent utilizes the backside of the substrate as an additional routing dimension, implementing power rails and signal routes on the backside that extend through vias to the frontside. This effectively doubles the available routing area without increasing the chip footprint, resolving the contradiction between routing simplicity and routing area availability.
2Area of stationary object
If feed-through via insertion is used to provide backside routing, then routing area increases, but device area penalty increases
Solution Approach 1:
The backside power rails serve multiple functions: they provide power delivery through the substrate, act as ground references, and enable backside signaling. This multi-functionality reduces the need for separate dedicated structures, thereby minimizing area penalties while maximizing routing area utilization.
3Manufacturing precision
If high cut metal gate density is used, then manufacturing precision improves, but parasitic resistance uniformity deteriorates
Solution Approach 1:
The patent implements localized dishing compensation techniques that apply different processing parameters to different regions of the substrate. By identifying areas with high cut metal gate density and applying targeted compensation, the system maintains manufacturing precision while restoring parasitic resistance uniformity in affected regions.
4Area of stationary object
If backside routing is implemented, then routing area efficiency improves, but device complexity increases
Solution Approach 1:
The routing system is segmented into distinct frontside and backside components, each optimized for specific functions. The backside primarily handles power delivery and ground references, while the frontside focuses on signal routing. This functional segmentation simplifies the overall design by reducing interdependencies and making each layer's optimization independent.
Data Source
AI summary
Analog circuit devices and methods are provided. An analog circuit device comprises a bottom metal routing layer comprising a plurality of tracks, an analog cell comprising an n-type metal oxide semiconductor (NMOS) active region and a p-type metal oxide semiconductor (PMOS) active region, a plurality of polysilicon layers, and a plurality of metal diffusion layers. In the analog device, the NMOS active region, PMOS active region, plurality of polysilicon layers, and plurality of metal diffusion layers make up a CMOS structure. The device further includes a plurality of guard ring cells surrounding the analog cell and a power rail structure configured to provide connection between the bottom metal routing layer and the analog cell.