Multilayer Chip Stacking Using Holding Sheets for Batch Joining
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Solution Overview
Problem
Conventional methods for manufacturing multilayer devices with stacked chips, such as COW and WOW, complicate the manufacturing process due to the need for repeated stacking operations and handling of thinned semiconductor wafers, which can lead to shear stress and breakage during polishing.
Innovation Solution
A method involving forming cutting sites on chip regions held by holding sheets, followed by a joining step where chip regions from two targets are stacked in a predetermined positional relationship, allowing all chip regions to be collectively joined in a single operation, thereby simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If chips are stacked one by one on N base regions according to the COW method, then individual chip stacking is achieved, but the stacking operation must be performed N times for the first layer and N×M times for M layers, greatly complicating the manufacturing process
Solution Approach 1:
The patent merges multiple individual chip stacking operations into a single batch operation. By forming cutting sites on chip regions while held by holding sheets and then joining multiple joining targets collectively, all chip regions are stacked simultaneously in one operation rather than requiring N separate stacking operations for the first layer alone.
Solution Approach 2:
The patent segments the manufacturing process into distinct phases: forming cutting sites on holding sheets, joining multiple targets collectively, and then separating individual chips. This segmentation allows the stacking operation to be performed once on multiple chips simultaneously, rather than stacking each chip individually multiple times.
2Ease of manufacture
If thinned semiconductor wafers are stacked on a base wafer according to the WOW method, then wafer stacking is achieved, but handling becomes technically difficult and shear stress occurs during polishing, risking breakage
Solution Approach 1:
The patent performs the joining operation before the thinning operation. By joining the semiconductor wafers while they are still at their original thickness, the wafers are easier to handle and less susceptible to breakage. The joining is completed prior to polishing, eliminating the risk of shear stress causing breakage during the polishing process.
Solution Approach 2:
The patent inverts the conventional sequence of operations. Instead of thinning first and then stacking (which causes handling difficulties and breakage risk), the patent stacks the wafers first at full thickness and then performs thinning. This reversal of the operation sequence eliminates the technical difficulties and reliability issues associated with handling and polishing thinned wafers.
3Reliability
If a thermal process is performed on a stack to enhance joining strength before polishing in the WOW method, then joining strength is improved, but the manufacturing process becomes more complex and time-consuming
Solution Approach 1:
The patent performs joining while wafers are at full thickness, which provides inherent mechanical strength and stability. This preliminary joining at optimal conditions eliminates the need for subsequent thermal processes to enhance joining strength, thereby simplifying the manufacturing process and reducing overall complexity.
Data Source
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AI summary
A method of manufacturing a multilayer device performs a first forming step, a second forming step, and a joining step. In the first forming step, a cutting site is formed at a first joining target provided with a plurality of chip regions while the first joining target is held by a first holding sheet. The cutting site is used for singulating the chip regions of the first joining target individually. In the second forming step, a cutting site is formed at a second joining target provided with a plurality of chip regions while the second joining target is held by a second holding sheet. The cutting site is used for singulating the chip regions of the second joining target individually. In the joining step, the first joining target and the second joining target are joined in such a manner that the respective chip regions of the first joining target and the second joining target are stacked on each other in a predetermined positional relationship therebetween by moving the first holding sheet and the second holding sheet relative to each other.