Gate Stack Support Layout for Uniform Contact Electrode Etching
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Solution Overview
Problem
The existing semiconductor devices face limitations in improving the degree of integration and reliability, particularly in non-volatile memory devices, due to challenges in the etching process for forming contact electrodes, which affects the electrical characteristics and productivity.
Innovation Solution
A semiconductor device design that includes a gate stack structure with alternately stacked interlayer insulating layers and gate electrodes, a channel structure extending through the gate stack, and a support structure for the contact electrode, which is electrically connected to the gate electrode and partially surrounded by the support structure, enhancing the etching process reliability and productivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the etching process for forming contact electrodes is performed in existing semiconductor devices, then the contact electrodes can be formed to connect gate electrodes, but the etching conditions are inconsistent leading to poor reliability and productivity
Solution Approach 1:
The gate electrode is divided into multiple segments along the third direction, with each segment having a corresponding contact electrode. The gate stack structure is segmented into repeating units, each comprising a gate electrode segment, contact electrode, and support structure portion. This segmentation allows the etching process to be performed on standardized, consistent structures, improving reliability while managing complexity through modular design.
Solution Approach 2:
The gate electrode extends in the third direction (vertical dimension) rather than only in the plane, creating a three-dimensional gate stack structure. This dimensional change enables multiple contact electrodes to connect to different segments of the gate electrode, improving reliability through redundant connection paths while the vertical segmentation maintains etching consistency.
2Quantity of substance
If the degree of integration of non-volatile memory devices is increased, then storage capacity improves, but challenges in the etching process affect productivity
Solution Approach 1:
The contact electrode is divided into multiple contact portions (first contact portion, second contact portion, etc.) along the third direction, with each portion corresponding to a specific gate electrode segment. This segmentation allows the etching process to create multiple connection points in a single manufacturing step, increasing storage capacity through higher integration while maintaining productivity through process efficiency.
Solution Approach 2:
The support structure serves multiple functions: it provides mechanical support for the contact electrode, defines the etching pattern, and ensures consistent etching conditions across all contact electrodes. This multi-functionality reduces the number of separate manufacturing steps needed, improving productivity while enabling higher integration.
3Manufacturing precision
If contact electrodes are formed without consistent etching conditions, then manufacturing is simpler, but electrical characteristics deteriorate
Solution Approach 1:
All gate electrode segments and contact electrodes are formed using the same etching process conditions, ensuring homogeneous etching results throughout the device. The repeating unit structure ensures that each contact electrode experiences identical etching conditions, achieving manufacturing precision without sacrificing simplicity, as the same process is applied uniformly across all features.
Solution Approach 2:
The gate stack structure and support structure are prepared in advance with precise dimensions and positions before the etching process. This preliminary preparation ensures that when the etching is performed, consistent conditions are automatically achieved, maintaining both manufacturing precision and simplicity by eliminating the need for complex real-time process control.
Data Source
AI summary
A semiconductor device includes a circuit region including a peripheral circuit on a substrate; and a cell region adjacent to the circuit region. The cell region includes a cell array region and a connecting region. The cell region also includes a gate stack that includes an interlayer insulating layer and a gate electrode, alternately stacked on the substrate; a channel in the cell array region that extends through the gate stack; a main support in the connecting region that extends through the gate stack; and a contact electrode in the connecting region connected to the gate electrode through the gate stack. The main support includes a first portion extending along a first direction; and a second portion extending from the first portion in a second direction crossing the first direction. At least a portion of the contact electrode is surrounded by the first and second portions of the main support.