BEOL Oxide Semiconductor NOT-Gate Stack for Low-Temperature Integration
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Solution Overview
Problem
There is a need for improved integration density and computing power in semiconductor devices without damaging previously fabricated components, particularly in the back-end-of-line (BEOL) processes, which can be achieved using oxide semiconductor-based transistors processed at low temperatures.
Innovation Solution
The development of semiconductor device structures incorporating a layer stack with a first and second conductivity-type semiconductor layers, dielectric isolation, and gate electrodes, formed using a BEOL process, enabling NOT-gate logic functions and integration with other BEOL circuit components like capacitors and inductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional high-temperature processing is used to improve integration density, then more components can be integrated, but previously fabricated FEOL and MEOL devices are damaged
Solution Approach 1:
The patent changes the temperature parameter of the processing method from conventional high-temperature processing to low-temperature processing (below 400°C). This allows BEOL integration of additional components while preventing thermal damage to previously fabricated FEOL and MEOL devices, resolving the contradiction between integration density and device integrity
Solution Approach 2:
The patent divides the semiconductor manufacturing process into distinct temperature zones: FEOL processing at high temperatures, followed by BEOL processing at low temperatures. This segmentation allows each stage to be optimized independently, enabling integration density improvement in BEOL without compromising FEOL device integrity
2Temperature
If oxide semiconductor-based transistors are used in BEOL processes, then low-temperature processing is enabled, but device complexity increases due to additional layers and structures
Solution Approach 1:
The patent employs oxide semiconductor material that serves multiple functions: it enables low-temperature processing, provides appropriate electrical characteristics for logic gates, and allows integration with standard BEOL dielectric materials. This multi-functionality reduces the need for specialized processing equipment and additional process steps, offsetting the increased structural complexity
Solution Approach 2:
The patent introduces a vertical stacking dimension with multiple dielectric layers (first dielectric layer, second dielectric layer, third dielectric layer) and embedded conductive elements. This three-dimensional integration approach achieves high functionality while maintaining planar process compatibility, managing complexity through vertical rather than lateral expansion
Data Source
AI summary
A semiconductor device structure providing a NOT gate logic function includes a layer stack including a pair of semiconductor layers having opposite conductivity-types, and a dielectric isolation layer disposed therebetween. First and second electrodes are located on a first side of the layer stack, where the first electrode contacts a first side surface of a first semiconductor layer and a second electrode contacts a first side surface a second semiconductor layer. A third electrode located on a second side of the layer stack contacts a second side surface of the first semiconductor layer and a second side surface of the second semiconductor layer. A gate dielectric layer is located over two side surfaces of the layer stack. A pair of gate electrodes located on either side of the layer stack contacts the gate dielectric layer. The semiconductor device structure may be fabricated using a BEOL process using metal-oxide semiconductor materials.